**5. Different internal and external fault detection by digital relay**

#### **5.1 LG faults**

LG faults have been applied at F1 to F7 locations as internal and external faults. Considered F1 fault as LG fault and used at 15 s of simulation time for 0.3 s duration which is an internal fault for W1. in this case-1, the voltages are unbalanced significantly which has V0/V1 ratio found 0.985pu which is greater than a set value and as per algorithm the relay issue tripping after 0.001 s which instantaneous. It is important to note that in this case, relay R2 at W2 and R3 at W3 are not affected and remain immune. The tripping coordination of R1 to R3 for this case-1 is shown in **Figure 6**. **Figure 7** shows that positive sequence and zero sequences are present significantly during the fault, and the ratio of V0/V1 exceeds the set value. Similarly, LG fault has been applied at the F6 location. In this case, the fault is at POC, which required the operation of all the relays operated at 0.2 s. **Table 2** shows the other faults and measurement of current and voltage sequence components during the faults at bus 1.

#### **5.2 LL faults**

As internal and external faults, LL faults have been applied at F1 to F7 locations. Considered F2 fault as LL fault and used at 15 s of simulation time for 0.3 s duration which is an internal fault for W2. In this case-2, the positive sequence voltages less than set value and as per the algorithm the relay issue tripping after 0.001 s. It is important to note that in this case, relay R1 at W1 and R3 at W3 are not affected

**Figure 6.** *Tripping of at W1, W2, and W3 while LG fault near bus 1.*

*An Algorithm for Default Detection of Wind Turbine Generators DOI: http://dx.doi.org/10.5772/intechopen.104793*

#### **Figure 7.** *Positive, negative, and zero sequence voltage variation during internal fault at W1.*


#### **Table 2.**

*Internal fault on feeder 1, 2, and 3 near SCIG.*

and remain immune. Additionally, It provides backup protection after 0.15 s and 0.14 s by R1 and R3 to R2. The V1 and V2/V1 variations are shown in **Table 2** during the LL fault at bus 2.

#### **5.3 LLG faults**

As internal and external faults, LLG faults have been applied at F1 to F7 locations. Considered F3 fault as LLG fault and used at 15 s of simulation time for 0.3 s duration which is an internal fault for W3. in this case-3, the positive sequence voltages less than set value and as per algorithm the relay issue tripping after 0.001 s. It is important to note that in this case, relay R1 at W1 and R3 at W3 are

not affected and remain immune. Additionally, It provides backup protection after 0.15 s and 0.14 s by R1 and R2 to R3.
