**6. Challenges and possibilities**

The main challenge in this protection scheme is that the relays R1 to R3 are affected by fault resistance while power swing occurs near them, and they cannot detect it. It is important to note that power swing blocking and out-of-step tripping functions are available to handle these challenges in the existing system [15].

### **7. Results and discussions**

The results of **Tables 2–4** clearly show the quantity such as instantaneous overload current (Ia, Ib, Ic), I1, I2/I1, V1, V2/V1, and V0/V1 changes during different faults differently. This variation is used in the digital relay to identify internal and external feeder faults. The relays at W1 to W3 remain immune due to correct settings during grid faults. In this protection scheme, instantaneous overload current (Ia, Ib, Ic) provides instantaneous AC Over current, I1 provides AC Overcurrent (positivesequence), I2/I1 provides Ac Current unbalance, V1 provides AC over and undervoltage (positive sequence), V2/V1 provides AC unbalance voltage (negative sequence), V0/V1 provides C unbalance voltage (zero sequences) protection to W1 to W3 against internal and external feeder faults correctly.

### **8. Conclusions**

F1 from F2 and F3 can be detected using positive sequence voltage because the fault current of F2 and F3 can be seen at W1 via step-up transformer and feeder, due to which current is reduced compared to F1 in case of LG fault. While W2 sees F2 directly and W3 sees F3 directly, that is not affected F1, which is a parallel feeder

fault. In the case of external fault, zero sequences cannot be used as they are trapped in the winding. So algorithm used negative sequence current and voltage to positive sequence current and voltage ratio, which is less than the set value in case of external fault. So, R1 to R3 does not operate. The proposed Algorithm based digital relay provides all the different fault detection in a single unit suitable for internal and external fault protection of WTG. The main challenge to this scheme is that fault resistance may mal-operate the scheme in some rare events.
