**5.4 LLLG faults**

LLLG faults have been applied at F1 to F7 locations as internal and external faults. Considered F4 fault as LLLG fault and used at 15 s of simulation time for 0.3 s duration which is the internal fault for W1. in this case-4, the positive sequence voltages less than set value and as per algorithm the relay issue tripping after 0.001 s. In this case, relay R2 at W2 and R3 at W3 is also instantaneous as the fault is on the point of Common Coupling (POC). **Table 3** shows that I2/I1 and V1 change significantly during fault at bus 4.
