**4. Experimental results and discussion**

The micro-architecture of the OIC is implemented using Verilog HDL and synthesised in ASIC and FPGA platforms to estimate hardware parameters (area, critical path delay, leakage power, dynamic power) and number of logical elements, register *Design of Low-Cost Reliable and Fault-Tolerant 32-Bit One Instruction Core for Multi-Core… DOI: http://dx.doi.org/10.5772/intechopen.102823*

usage respectively. In the Section 4.1, comparison of area, power, registers and number of logical elements of OIC with an approach named URISC proposed by [19] and URISC ++ proposed by [20] is presented. Notably, URISC/URISC++ implement one instruction set. The URISC/URISC++, a co-processor for TigerMIPS, emulates instructions through the execution of subleq instruction. TigerMIPS performs static code insertion in both control flow and data flow invariants so as to detect faults by performing repeated executions of subleq within the co-processor. Comparative analysis on hardware parameters for different modes of OIC are discussed in Section 4.2.

**ASIC simulation:** The OIC given in **Figure 2** and multi-core system in **Figure 3** has been implemented using Verilog HDL and then synthesized in Cadence Encounter (R) RTL Compiler RC14.28 –V14.20 (Cadence design systems 2004) using TSMC 90 nm technology library (tcbn90lphptc 150). The area, power (dynamic, leakage, net, internal) and critical path delay are estimated for the OIC and tabulated in **Table 2**.

**FPGA synthesis:** The OIC is synthesized using Quartus prime Cyclone IVE with device EP4CE115FE29C7 and the results are illustrated in **Tables 3** and **4**.

**Leakage power and dynamic power:** Power dissipation shown in **Table 2** is understood as sum of dynamic power and static power (or cell leakage). Static power is consumed when gates are not switching. It is caused by current flowing through transistors when they are turned off and is proportional to the size of the circuit. Dynamic power is a sum of net switching power and cell internal power. The net switching power is the power dissipated in the interconnects and the gate capacitance.


#### **Table 2.**

*Implementation of 32 bit OIC results using 90 nm TSMC technology.*


**Table 3.** *FPGA synthesis results for OIC.*


#### **Table 4.**

*FPGA synthesis results comparison.*

The cell internal power is the power consumed within a cell by charging and discharging cell internal capacitances. The total power is a sum of the dynamic power and the leakage power.

**Multi2sim (version 5.0):** Multi2sim supports emulation for 32 bit MIPS/ARM binaries and simulation for 32-bit 86 architectures. It performs both functional and timing simulations. The performance loss is estimated for compute intensive and memory intensive micro-benchmarks using a Multi2sim simulator. Performance loss for micro-benchmarks listed in **Table 6** are illustrated in **Figures 6**–**11**.

#### **4.1 Comparative analysis: power, area, registers and logical elements**

With the critical path delay at 8608 ps, the operating frequency of the circuit is 115 MHz with power supply at 1.2v. OIC is a low power core consuming 1.3 mW, with die area of 8122 μm<sup>2</sup> . The die area of conventional MIPS core is 98,558 <sup>μ</sup>m<sup>2</sup> which is 14.2 larger than OIC core. The MIPS core consumes a total power of 1.153 W and the 32-bit OIC consumes 1.39 mW; order of difference in powers of 10 is three. The registers in OIC are PC and temporary registers which hold the operands. But they are not designed and managed as a register file. **Tables 3** and **4** provide the register count and logical elements count for OIC and URISC++. The number of logical elements in OIC is 3.51% and 3.52% of the logical elements in URISC and URISC++ respectively. The number of registers in OIC is 3.05% of URISC++. URISC++ adds 62 logical elements and one additional register to the architecture of URISC. The logical elements in URISC++ consume 6.6 mW. URISC++ has 650 registers or 14.3% of registers in TigerMIPS. URISC++ has two large register files. URISC++ altogether consumes 1.96 W. Thus, OIC consumes less power than URISC++.

#### **4.2 Comparative analysis: four modes of OIC**

The critical path delay, area, dynamic power and leakage power for the four modes of OIC namely baseline mode, DMR mode, TMR mode and TMR + SCS mode are normalized to baseline mode and shown in **Figure 5**. The area overhead of TMR + SCS mode is 68.43% of the baseline, area overhead of TMR mode is 65.37% of the baseline and for DMR mode it is 51.4%. The comparators and subtractors occupy 22.71% and 28.6% of TMR + SCS mode area respectively. The size of the voter is negligible in TMR + SCS mode and TMR mode. In the critical path delay, 10% increase is noticed from the baseline to TMR + SCS mode. The critical path traverses from the subtractor input to the comparator, and then to the voter, passing through select logic and ends at an input line. Delay would not differ much between TMR mode and TMR + SCS mode.

Both the dynamic power and leakage power for TMR mode and DMR mode increase significantly due to redundant subtractors and comparators which are not in the baseline. The dynamic power overhead of TMR mode and DMR mode is 60% and *Design of Low-Cost Reliable and Fault-Tolerant 32-Bit One Instruction Core for Multi-Core… DOI: http://dx.doi.org/10.5772/intechopen.102823*

**Figure 5.**

*(a) Area, (b) critical path delay, (c) leakage power and (d) dynamic power (*y*-axis—normalized values to baseline).*

73% of the baseline. It is 75% for TMR + SCS mode. The static power or leakage power is proportional to the size of the circuit. The TMR + SCS mode has leakage power which is 76% more than the baseline. The TMR and DMR mode have leakage power which is 72% and 50% more than the baseline. In **Table 4** which depicts FPGA synthesis results, it is observed that the number of logical elements in TMR + SCS mode and DMR mode is 79% and 66% more than the baseline. From **Tables 2** and **4**, it is observed that TMR mode with additional self-checking subtractor in TMR + SCS mode costs more than the baseline, but still TMR + SCS/OIC will be a suitable fault tolerant core for a low power embedded system.

#### **4.3 Power and area estimation for MCS-OIC**

The area and power for the micro-architecture of multi-core system (one MIPS core with one OIC) shown in **Figure 3**, are estimated using ASIC simulation. The multi-core system occupies a total area of 306,283 μm<sup>2</sup> and consumes a total power of 1.1554 W. The FDL occupies an area of 6203 μm<sup>2</sup> which is 2% of the total area occupied by the system. The OIC occupies an area of 8122 μm2 which is 2.6% of the total area occupied by the system. The FDL consumes a power of 1.2 mW and OIC consumes a power of 1.4 mW which are negligible when compared to the total power. The redundancy-based core level fault mitigation techniques/approaches such as Slipstream [21], dynamic core coupling (DCC) approach proposed by [22], configurable isolation [23], reunion is a fingerprinting technique proposed by Smolens et al. [24] have nearly 100% area overhead and obviously larger power overhead.

#### **5. Performance implications in MCS-OIC**

For every instruction emulated on OIC, an additional three clock cycles are needed for transfer of opcodes and operands, and two clock cycles are needed to resume the

pipeline in the MIPS processor. The two terms defined below highlight the latency that incur in instruction execution, presented in the following subsection.

#### **5.1 Performance overhead at instruction level**

**Definitions:** (a) The **instruction execution time by emulation (IETE)** is defined as the number of cycles needed to execute the instruction on OIC. (b) **Total execution time (TET)** is defined as the sum of IETE and time (in clock cycles) to transfer opcodes, operands (from MIPS to OIC) and results (from OIC to MIPS). In other words, this indicates that time in clock cycles between pipeline stall and resumption of pipeline. The TET and IETE for instructions are tabulated in **Table 5**.

#### **5.2 Performance overhead at application level**

In the previous section, performance loss at instruction level caused due to transfer of operands and results back to host core is discussed. This would cause an accumulative loss in performance of application and the same is discussed in this section. The OIC supports 32 bit ISA of MIPS R3000/4000 processor operating at a frequency of 250 MHz. OIC operates at a frequency of 115 MHz, thereby incurring a performance loss while emulating the instructions from a faulty functional unit in MIPS core. The Multi2sim, a cycle accurate simulator together with a cross compiler, *mips-linux-gnu-gcc/mips-unknown-gnu-gcc* is used to estimate the simulation execution time for a set of micro-benchmarks. The emulation of only arithmetic instructions on OIC is considered for estimating the performance loss as they constitute nearly 60% of total instructions in integer application programs. The compute intensive and memory intensive micro-benchmark programs considered are listed in **Table 6**.

#### *5.2.1. Memory intensive micro-benchmarks*

The performance loss for memory intensive micro-benchmark programs, namely, binary search, quicksort (using recursion), and radix sort, are given in **Figures 6**–**8** respectively. The performance loss for CPU intensive micro-benchmark programs, namely, matrix multiplication, CPU scheduling, and sieve of Eratosthenes, are given in the **Figures 9**–**11** respectively. The baseline indicates the simulated execution time


**Table 5.** *IETE and TET for instructions.* *Design of Low-Cost Reliable and Fault-Tolerant 32-Bit One Instruction Core for Multi-Core… DOI: http://dx.doi.org/10.5772/intechopen.102823*


#### **Table 6.**

*CPU intensive and memory intensive micro-benchmarks.*

**Figure 6.** *Performance overhead in binary search by emulating ADD using subleq instruction.*

of micro-benchmarks with no arithmetic instructions emulated on OIC. The performance loss is quantified for micro-benchmarks with respect to simulated execution time of the baseline (with varying input data sets/size).

As shown in **Figure 6**, Binary search with emulation of ADD instructions incurs performance loss of 1.77, 3.59 and 4.59 with input size of 3000, 30,000 and 300,000 respectively, when compared to baselines. Significant proportion of ADD instructions is associated with incrementing or decrementing counters and effective addresses. OIC do not fetch operands or store results directly to main memory. Main memory latency is not taken into account for performance loss estimation. The number of ADD instructions executing as a part of the algorithmic phase of program execution does not increase exponentially with increase in input data sets. Hence, performance loss impact is minimal in algorithmic phase and is higher during fetching and storing of the input data sets. In case of multithreaded binary search, multi-core setup consisting of two cores core-0 and core-1 each with single thread is used to estimate the performance loss. The performance loss is similar to that of single

**Figure 7.** *Performance overhead in Quicksort by emulating ADD using subleq instruction.*

**Figure 8.**

*Performance overhead in Radix sort by emulating ADD and DIV using subleq instruction.*

threaded binary search. It is due to the fact that majority of the ADD instructions are associated with LOAD and STORE instructions.

Quicksort (with emulation of ADD instruction), implemented using recursion for sorted data elements (worst case analysis) incurs performance loss of 3.85, 6.31, and 6.99 for data size of 100, 1000 and 10,000 respectively as shown in **Figure 7**. For best case analysis of quicksort for 10,000 elements, performance loss reduces to 1.008. Due to recursion, majority of ADD instructions are associated with LOAD/ STORE instructions. In radix sort, occurrence of ADD instructions is more compared to DIV instructions. Since it is memory intensive method of sorting, large number of

*Design of Low-Cost Reliable and Fault-Tolerant 32-Bit One Instruction Core for Multi-Core… DOI: http://dx.doi.org/10.5772/intechopen.102823*

ADD instructions is used to increment counters and constants associated with LOAD/ STORE instructions. The performance loss due to emulation of ADD instructions for radix sort is 2.45, 4.79, and 5.96 for input sizes of 1000, 10,000 and 10,000 as shown in **Figure 8**. For DIV instructions, performance loss is 1.4, 2.05, and 2.37 for input sizes of 1000, 10,000 and 10,000 elements.

As shown in **Figure 9**, matrix multiplication with emulation of ADD and MUL instructions executing in the algorithmic phase of the program, incurs a performance loss of <1.56, 4.09, 4.0> (for ADD) and <1.632, 7.62, 7.99> (for MUL), for input matrix sizes of 10 10, 100 100, and 1000 1000 respectively. In CPU scheduling, ADD and SUB instructions emulation incur a performance loss of <2.45, 4.79, 5.96> and <1.4, 2.05, 2.3> for input data set of 1000, 10,000 and 100,000 processes respectively as shown in **Figure 10**. In sieve of Eratosthenes, emulation of MUL and ADD instructions incur a performance loss of <1.89, 5.03, 7.63> and <1.48, 2.9, 3.8> for input data set size of 1000, 10,000 and 100,000 respectively as shown in **Figure 11**.

**Figure 9.**

*Performance overhead in matrix multiplication by emulating ADD and MUL using subleq instruction.*

**Figure 10.**

*Performance overhead in CPU scheduling by emulating ADD and SUB using subleq instruction.*

**Figure 11.** *Performance overhead in Sieve of Eratosthenes by emulating MUL and ADD using subleq instruction.*

For multithreaded matrix multiplication, multi-core configuration consisting of two cores: core-0 and core-1 with single thread each is considered. The ADD and MUL instructions of core-0 and core-1 are emulated on single OIC due to failures in adder and multiplier units respectively. The performance loss is estimated as 2.04, 10.07, and 10.99 for matrix size of 10 10, 100 100, and 1000 1000 respectively as shown in **Figure 9**. Since, simultaneous access to single OIC from two cores is not permitted, performance loss includes the waiting time between subsequent ADD and MUL instructions emanating from core-0 and core-1. Waiting time alone is greater than 45% of the performance loss. In this multi-core configuration, consisting of two MIPS cores with single OIC, it bears the brunt of multiple functional unit failures in two cores. An Additional OIC would bring down the performance loss by 1.5 (for matrix size of 10 10) and 7 (for matrix size of 100 100/1000 1000) and eliminate the need for instructions to wait for execution on OIC. On 1:1 and 1: N basis i.e., one MIPS core with one or more OICs can scale to 100 MIPS core with 100 or more OICs.

It may be noticed that the performance loss does not vary when there is change of mode in OIC from TMR + SCR to TMR, or TMR to DMR as the number of instructions executed remains the same.

### **6. Yield analysis for MCS-OIC**

This section examines the effect of fault tolerance provided in MCS-OIC on the yield. As discussed in the section which presents design of OIC, it is assumed that two subtractors do not fail simultaneously. In the TMR + SCR, TMR, and DMR modes, OIC repeats the instruction execution if the results differ, to avoid transient failures. The spatial and temporal redundancy to avoid permanent and transient faults in OIC makes it defect tolerant. The arithmetic logic unit in MIPS is protected by functional support provided by OIC. The remaining portion of MIPS are hardened and protected by ECC. The die yield for proposed different configurations of MCS-OIC is estimated using the equations presented below.

*Design of Low-Cost Reliable and Fault-Tolerant 32-Bit One Instruction Core for Multi-Core… DOI: http://dx.doi.org/10.5772/intechopen.102823*

#### **6.1 Terms and parameters**


$$\text{Regular dies per wafter} = \frac{\pi (\text{diameter}/2)^2}{\text{Area}} - \frac{\pi \times \text{diameter}}{\sqrt{2} \times \text{Area}} \tag{1}$$

Where diameter refers to the diameter of the wafer, Area refers to the area of the die.

d. *Die yield*: Ignoring full wafer damage, the yield for single die is approximated using negative binomial approximation as given in the Eq. (2).

$$|Die\;yield = \left(1 + \frac{\text{defect density} \times \text{Area}}{\text{cp}}\right)^{-\text{cp}}\tag{2}$$

Where cp denotes cluster parameter or manufacturing complexity, defect density denotes number of defects per unit area.

e. *Regular working dies per wafer*: It is die yield times the regular dies per wafer. It is estimated using the Eq. (3).

$$\begin{aligned} \text{Regular working dies per wafer} &= \left( 1 + \frac{\text{defect density} \times \text{Area}}{\text{cp}} \right)^{-\text{cp}}. \\ \left( \frac{\pi (\text{diameter}/2)^2}{\text{Area}} - \frac{\pi \times \text{diameter}}{\sqrt{2} \times \text{Area}} \right) \end{aligned} \tag{3}$$

#### f. *Regular fault tolerant dies per wafer*:

The area of fault tolerant core is expressed as summation of area of original die and area of OIC. If the area of OIC is expressed as *δ*ð Þ 0< *δ*< 1 times the area of original design then ((1 + *δ*) � area of the original design)) denotes the area of the fault tolerant die. By substituting (1 + *δ*) � area in the number of regular fault tolerant cores per wafer can be estimated and is given in the Eq. (4).

$$\text{Regular fault tolerance per water} = \frac{\pi(\text{diameter}/2)^2}{(1+\delta)\text{Area}} - \frac{\pi \times \text{diameter}}{\sqrt{(2}\ (1+\delta)\text{ Area})} \tag{4}$$

g. *Regular working fault tolerant dies per wafer*: It is die yield times the regular fault tolerant die. It is estimated using the Eq. (5).

$$\text{Regular working fault tolerance per wafer} = \left( 1 + \frac{\text{defect density} \times \text{Area}}{\text{cp}} \right)^{-\text{cp}}.$$

$$\left( \frac{\pi (\text{diameter}/2)^2}{(1+\delta)\text{Area}} - \frac{\pi \times \text{diameter}}{\sqrt{(2}(1+\delta)\text{Area})} \right) \tag{5}$$

#### **6.2 Parametric evaluation and discussion**

The die yield for the original die and fault tolerant die estimated for one MIPS core with one/two/four/ OICs, two MIPS core with one/two/four/ OICs, four MIPS core with one/two/four/ OICs, and eight MIPS core with one/two/four/six OICs is tabulated in **Tables 7**–**10** respectively. The defect density is varied from 9.5, 5.0, to 1.0 and wafer diameters varied from 300 mm, 200 mm to 100 mm to estimate die yield of the original die and fault tolerant die. The cp is fixed at 4.0. The die yield of the original die at defect densities are 1.0, 5.0, and 9.5 are 0.9971, 0.9855, and 0.9727 respectively. The die yields for three fault tolerant dies each consisting of one MIPS core with first die with one OIC, second with two OICs, third with four OICs for 300 mm wafer with defect density at 1.0 is <0.9970/0.9969/0.9967> respectively as shown in the **Table 7**, which is slightly lesser than the yield of the original die. The average of the differences between yield of original die and fault tolerant dies with defect density 1.0 is 0.0002 which is negligible value. Similarly, the average of the differences between yield of original die and fault tolerant dies at defect density 5.0 and 9.5 are 0.0009 and 0.0017 respectively. It is observed that an increase in the defect density decreases the yield.


**Table 7.** *Die yield for fault tolerant die consisting of one MIPS core with one/two/four OICs.*

*Design of Low-Cost Reliable and Fault-Tolerant 32-Bit One Instruction Core for Multi-Core… DOI: http://dx.doi.org/10.5772/intechopen.102823*


#### **Table 8.**

*Die yield for fault tolerant die consisting of two MIPS core with one/two/four OICs.*

The die yield of the fault tolerant dies each consisting of two MIPS cores with < one/two/four> OICS with defect density 1.0 is <0.9941, 0.9940, 0.9937> respectively as shown in **Table 8**. The die yield of the original die at defect densities 1.0, 5.0, and 9.5 is 0.9942, 0.9713, and 0.9463 slightly higher than yield of fault tolerant dies. The average of the differences between yield of original die and fault tolerant dies is 0.00026. The average of the differences between yield of original die and fault tolerant dies increases by 0.0009 and 0.0018 for defect density 5.0 and 9.5 respectively.

The die yields of the original die at defect densities 1.0, 5.0, and 9.5 are 0.9884, 0.9436, and 0.8963 respectively. From **Table 9**, the die yield of the fault tolerant dies each consisting of four MIPS cores with <one/two/four> OICS with defect density 1.0 are <0.9883, 0.9882, 0.9880> respectively. It is observed that average of the differences between yield of the original die and fault tolerant dies at varying defect densities is similar with other alternatives discussed above.

From **Table 10**, the die yield of the fault tolerant dies each consisting of eight MIPS cores with <one/two/four/six> OICS with defect density 1.0 is <0.9769, 0.9767, 0.9765, 0.9764> respectively. The die yield of the original die at defect densities 1.0, 5.0, and 9.5 is 0.9769, 0.8912, and 0.8057 respectively. The average of the differences between the original die and fault tolerant dies with defect density of 9.5 is 0.0031, is the highest among the averages. From this data, it is inferred that larger chips with increasing redundancy widens gap between the yield of the original dies and fault


#### **Table 9.**

*Die yield for fault tolerant die consisting of four MIPS core with one/two/four OICs.*


**Table 10.**

*Die yield for fault tolerant die consisting of eight MIPS core with one/two/four/six OICs.*

*Design of Low-Cost Reliable and Fault-Tolerant 32-Bit One Instruction Core for Multi-Core… DOI: http://dx.doi.org/10.5772/intechopen.102823*

tolerant dies. Thus, a trade-off exists between the die yield and fault tolerance provided by the design alternatives (discussed above) having redundancy ranging between 2% and 11%.

#### **7. Reliability analysis of 32-bit OIC**

In order to assess the endurance for the four modes of OIC, reliability is evaluated and compared. The reliability, denoted by *R*(t), is defined as the probability of its survival at least until time t, which is estimated using Weibull distribution and can be determined in the following manner:

$$R(t) = P(T > t) = e^{-\lambda t^{\beta}} \tag{6}$$

where *β* is the shape parameter,*T* denotes the lifetime and *λ* denotes the failure rate of a component. Defect induced faults occur in the early stage of the lifetime, but the wear-out induced faults increase in the tail end of the lifetime. *β* < 1, is used to model infant mortality and it is a period of growing reliability and decreasing failure rate. When *β* = 1, the *R*(t) of Weibull distribution and exponential distribution are identical. *β* > 1, is used to model wear out and the end of useful life where failure rate is increasing. The initial failure rate is computed using the failure rate formula:

$$
\lambda = (\mathbf{C}\_1 \boldsymbol{\pi}\_\mathrm{T} \boldsymbol{\pi}\_\mathrm{V} + \mathbf{C}\_2 \boldsymbol{\pi}\_\mathrm{E}) \boldsymbol{\pi}\_\mathrm{Q} \boldsymbol{\pi}\_\mathrm{L} \tag{7}
$$

here, *C*1,*C*<sup>2</sup> are the complexity factors, *π*T, *π*V, *π*E, *π*<sup>Q</sup> , *π*<sup>L</sup> are temperature, voltage stress, environment, quality and learning factors respectively. Failure rate *λ* is assumed as a function of the number of logical elements in the micro-architectural components.

The reliabilities of the four modes of OIC given in the Eqs. (8)�(11) are expressed in terms of *R*select logicð Þ*t* , *R*subð Þ*t* , *R*sub�scð Þ*t* , *R*compð Þ*t R*voter which denote the reliabilities of select logic, subtractor, SCS, comparator and voters logic respectively.

TMR + SCS mode reliability is expressed as:

$$R\_{\text{TMT}+\text{SCS}}(t) = R\_{\text{sub}-\text{sc}}(t)R\_{\text{select logic}}(t)R\_{\text{comp}}(t)R\_{\text{veter}}(t)\sum\_{i=2}^{4} \binom{4}{i} \left(R\_{\text{sub}}(t)\right)^{i} \left(1 - R\_{\text{sub}}(t)\right)^{4-i} \tag{8}$$

TMR mode reliability is expressed as:

$$R\_{\rm TMR}(t) = R\_{\rm select \, logic}(t) R\_{\rm comp}(t) R\_{\rm voter}(t) \sum\_{i=2}^{3} \binom{3}{i} \left( R\_{\rm sub}(t) \right)^{i} \left( 1 - R\_{\rm sub}(t) \right)^{3-i} \tag{9}$$

DMR mode reliability is expressed as:

$$R\_{\rm DMR}(t) = R\_{\rm select\ logic}(t) R\_{\rm comp}(t) \sum\_{i=1}^{2} \binom{2}{i} \left(R\_{\rm sub}(t)\right)^{i} \left(1 - R\_{\rm sub}(t)\right)^{2-i} \tag{10}$$

Baseline mode reliability is expressed as:

$$R\_{\text{baseline}}(t) = R\_{\text{select logic}}(t) R\_{\text{sub}-\text{sc}}(t) \tag{11}$$

The reliabilities are plotted for TMR + SCS, TMR, DMR and Baseline modes in **Figure 12** for *β* = 0.9 and 1.0, (which denote defect induced fault phase) and in **Figure 13** for *β* = 1.1 and 1.2 (which denote wear out induced fault phase). *λ* is a function of number of logical elements as given in the **Table 3**.

In all these cases, TMR + SCS mode is observed to have a better failure tolerance when compared to all other modes. For *β* = 1.2, the reliabilities of TMR mode and DMR mode are less than that of TMR + SCS mode during the interval 3 � <sup>10</sup><sup>4</sup> to <sup>15</sup> � <sup>10</sup><sup>4</sup> hours, as illustrated in **Figure 13**. The levels of reliability of TMR modes decline far below DMR, and baseline modes in wear out induced fault phase due to the

**Figure 12.** *Reliability vs. time for (a)* β *= 0.9 and (b)* β *= 1.0.*

*Design of Low-Cost Reliable and Fault-Tolerant 32-Bit One Instruction Core for Multi-Core… DOI: http://dx.doi.org/10.5772/intechopen.102823*

**Figure 13.** *Reliability vs. time for (a)* β *= 1.1 and (b)* β *= 1.2*

fact that a single component reliability is below 0.5 and that the redundancy does not have any merit in the TMR mode. In **Table 11**, reliability of subtractor goes below 0.5 at *t* = 180,000 h or 20.5 years and reliability gap between TMR and DMR widens endorses the above argument.

#### **7.1 Comparative analysis: OIC and URISC/URISC++**

In this section, reliability of OIC is compared with that of URISC++. The reliability function of Weibull distribution with λ as a function of number of logical elements is used to estimate the reliability of URISC/URISC++. The number of logical elements in

#### *Quality Control - An Anthology of Cases*


**Table 11.**

*Reliabilities of components in OIC for* β *= 1.2.*

**Figure 14.** β *= 0.9 reliability vs. time (hours).*

β *= 1.0 reliability vs. time (hours).*

OIC and URISC++ are given in **Table 4**. In the defect induced fault phase (*β* = 0.9 and *β* = 1.0), a drastic fall in the URISC++ reliability is observed as shown in **Figures 14** and **15**. OIC continues to maintain a reliability of 0.96, unlike URISC++ with endurance reaching 0.87 after 210,000 hours. In the wear-out induced fault phase, the

*Design of Low-Cost Reliable and Fault-Tolerant 32-Bit One Instruction Core for Multi-Core… DOI: http://dx.doi.org/10.5772/intechopen.102823*

**Figure 16.**

β *= 1.1 reliability vs. time (hours).*

**Figure 17.** β *= 1.2 Reliability vs. time (hours).*

reliability gap widens between 32-bit OIC and URISC++ when *β* = 1.1 (**Figure 16**) after 60,000 hours or 6.84 years. The reliability levels of OIC fall below that of URISC++ because single component reliability reduces below 0.5 after 23.4 years as shown in **Figure 17** and the redundancy in the OIC does not have any merit thereafter.
