**2.1 Chapter contributions**

Contributions of the chapter are briefly presented below.


#### **2.2 Chapter organization**

The remaining portion of the chapter is organized as follows as: Section titled "3. An Overview on 32-bit OIC" presents (a) an outline of 32-bit OIC (b) one instruction set of OIC (c) modes of operation of OIC (d) microarchitecture of OIC (e) microarchitecture of multi-core system consisting of OIC (f) instruction execution flow in multi-core system using one instruction cores (MCS-OIC); Section titled "4. Experimental results and discussion" presents power, area, register and logical elements estimation for OIC, and power, area estimation for MCS-OIC; Section titled "5. Performance implications in multi-core systems" presents performance implications at instruction level and application level; Section titled "6. Yield analysis for MCS-OIC" presents yield estimates for the proposed MCS-OIC; Section titled "7. Reliability analysis of 32-bit OIC" presents reliability modelling of OIC and its estimate in different operational modes; the conclusion of the chapter is presented in the Section titled "8. Conclusion"; the relevant references are citated in the Section titled "References".
