**1. Introduction**

Researchers have predicted about an eight percent increase in soft-error rate per logic state bit in each technology generation [1]. According to the International Telecommunication Roadmap for Semiconductors (ITRS) 2005 and 2011, reduction in dynamic power, increase in resilience to faults and heterogeneity in computing architecture pose a challenge for researchers. According to the International Roadmap for

**Figure 1.** *SERs at various technology node.*

Device and System (IRDS) roadmap 2017, device scaling will touch the physical limits with failures reaching one failure per hour as shown in **Figure 1**. The soft error rate (SER) is the rate at which a device or system encounters or is predicted to encounter soft errors per unit of time, and is typically expressed as failures-in-time (FIT). It can be seen, from **Figure 1** [2–4] that, at 16 nm process node size, a chip with 100 cores could come across one failure every hour due to soft errors.

This decrease in process node size and increase in integration density as seen in **Figure 1**, has the following effects.


This scenario can be envisaged as a "fault wall". In order to surmount the fault wall scenario, reliability has been identified as a primary parameter for future multi-core processor design [9, 10]. Similarly, ITRS 2005 and 2011, have also identified increase in resilience to faults as a major challenge for researchers. Hence, a number of researchers have started focusing on resilience to faults and reliability enhancement in multi-core processors. The chapter focuses on providing fault tolerance solutions for processor cores in multi-core systems.

*Design of Low-Cost Reliable and Fault-Tolerant 32-Bit One Instruction Core for Multi-Core… DOI: http://dx.doi.org/10.5772/intechopen.102823*
