**4.3 Signal processing overview**

The algorithm for signal evaluation is implemented on a field-programmable gate array (FPGA) to facilitate real-time processing. A parallel signal processing and control of all peripheral units such as ADC, DAC, radar, data transmission interface (USB), etc., are set up. The signal processing starts with the FMCW ramp

**Figure 3.** *View of the FMCW radar.*

*Intelligent Mine Periphery Surveillance Using Microwave Radar DOI: http://dx.doi.org/10.5772/intechopen.100521*

generation inside the FPGA using very high description language (VHDL) software. This ramp is converted from digital data to analog with a DAC and is amplified. Finally, it reaches the radar interface FMCW transceiver. The transceiver, using the ramp, generates a modulated signal to transmit it. Then the signal is reflected by some targets and is received by each receiver antenna, and then the calculation of beat signals is done. Thus, the beat signal is amplified and converted from analog to digital data with an ADC to adapt measured signals to the FPGA. This block contains digital to analog (or vice versa) conversions, amplification, and FPGA processing. The ramp generated in the FPGA is then sent to a 16 bit digital to analog converter (DAC). The FMCW radar uses the ramp information to emit a transmitted signal, which is used to obtain the beat signal by mixing with the received one. Fast Fourier transform (FFT) is primarily used for signal processing.

The presence and distance of targets are identified by identifying the peaks. The signal processing is achieved on-board entirely by the microcontroller with ARM Cortex-M4F core, a group of 32-bit reduced instruction set computer (RISC) based ARM processor cores. The cores, when intended for micro-controller use, consist of the Cortex-M4F core features SIMD type instructions (single instruction, multiple data) and the floating-point unit, which, combined with high operating frequency, 32-bit hardware multiplies with the 64-bit result, 12 cycles interrupt latency results in very efficient data handling. The FFT composed of 1024 samples of singleprecision (32 bit) floating-point type is calculated slightly less than 5 ms. The ARM Cortex-M4F processor is very well appropriated for mainly deterministic real-time applications, even for low-cost platforms [30–33]. Microprocessor algorithms provide powerful digital signal processing to identify the digital signature of intruders walking, automotive, etc., through the detection range. Intruders entering the detection zone are monitored in real-time. Signal processing using application software in the periphery surveillance system is mainly consists of software design, pre-processing, computation, FFT, graphical interface, and control module [33–36].

## **4.4 Digital oscilloscope measurement**

**Figure 4** shows the radar waveform received from the digital oscilloscope. These are raw data received from the FMCW radar. There are two different lines in the

**Figure 4.** *Output radar signal graph from the oscilloscope.*

**Figure 5.**

*Flow chart of intelligent mine periphery surveillance system implementation process used in the FMCW radar.*

A-scope graph, viz. the yellow line and the red line. The yellow line represents the data after DSP signal processing in the distance domain. Red line is the user configured threshold to cancel out noise detection. Based on the above, the radar application gives alarm for the distance domain. The signal program the user-configured threshold set value 250 to cancel out noise detection, and object target 5 m and distant object 10 m. The flow chart of the function of the periphery surveillance system implementation process used in the FMCW radar, PTZ camera, and wireless sensor network has been shown in **Figure 5**.
