**5. Recent study of noises in tunnel FETs**

The electrical noise analysis especially the low-frequency noise analysis of TFET structure has been done by many researchers from universities and electronic companies. But the high-frequency analysis of TFET is yet to be explored a lot. In the past a few years, the research of various TFET structures has been accelerated. The brief review of impact of noise on various TFET structure is presented in this section.

The impact of single acceptor-type and donor-type interface trap induced RTN on TFET was reported in [32]. Using a charge-based approach, an analytical model for thermal noise and induced gate noise was proposed in junctionless FETs, whereas the power spectral density of noise was the same for the same drain voltage [33]. Neves et al. reported the effect of low-frequency noise on the behavior of vertical tunnel FETs (TFETs) experimentally and compared with MOSFET [34]. Chen et al. reported the amplitude of RTN on the characteristics of TFET experimentally and reveals that nonuniform distribution of BTBT generation rate along device width direction is responsible for high-amplitude of RTN. It also shows the high source doping concentration fluctuates the BTBT generation rate and reduces the RTN amplitudes [35]. High-frequency noise shows different behavior for the devices having different gate lengths. The scaling of gate length of the Highelectron-mobility-transistor (HEMT) was performed in [36]. **Figure 3** shows the change in the value of the noise suppression factor by changing length.

Ghosh et al. presented analysis of flicker noise of TFET structure. A selective buried oxide (SELBOX) SiGe layer has been used at the source channel junction in the presence of trap concentrations as shown in **Figure 4a**. In **Figure 4b**, the presence of trap degrades both ON–OFF current ratio and SS has been studied. Thus, it degrades the overall performance of the device [37].

**Figure 3.** *Gate length vs. noise suppression factor [36].*

**Figure 4.**

*(a) Proposed SELBOX structure, (b) effect of change in trap concentrations on ON–OFF current ratio and SS [37].*

S.Y. Kim et al. reported the dependency of low frequency noise on the applied gate voltage of TFET device. At low gate voltage, the noise in TFET is high and for high gate voltage, electrons directly tunnel from source to drain and noise in TFET is low [38].

Another noise analysis of Ferroelectric Dopant Segregated Schottky Barrier TFET has been done for different types of materials in the dopant segregated layer and concluded that flicker noise affects the low frequency and mid-frequency range [39].

#### **6. Noise in Si/Ge tunnel FETs**

The conventional Si-based TFET exhibits SS of less than 60 mV/decade and a very small leakage current but practically implementation is still questionable because of low ON current. Thus, to improve the ON current, a thin layer of SiGe can be used on top of the Si source. It is found from, study that the proposed device is free from short channel effects. Using the strained SiGe layer improves on current while leakage current was still very low (fA) [40]. In **Figure 5**, the proposed TFET structure with a strained SiGe layer is shown.

The features like VLSI compatibility, mature synthesis techniques, and tunable bandgap makes SiGe compatible with the TFET structure. Li et al. experimentally demonstrated a TFET structure in which a thin layer of SiGe is inserted between source and channel. By using the SiGe layer, it has been found that the ON current increases and SS reduces. The barrier height of tunneling reduces and the lateral electric field increases that further increases the transport of carriers across tunneling junction. The performance of the proposed TFET device has been improved by using SiGe [41].

Vandooren et al. presented the electrical performance of vertical Si homojunction and SiGe source hetero-junction TFETs. The analysis of trap-assisted tunneling through simulations and characterization has been performed. The trap-assisted tunneling worsens the onset characteristics and SS of the TFET. The simulation results of Ge TFET are in agreement with experimental data up to some

**Figure 5.** *TFET structure with strained SiGe layer [40].*

#### *Noise Analysis in Nanostructured Tunnel Field Devices DOI: http://dx.doi.org/10.5772/intechopen.100633*

extent. The results demonstrated that SiGe TFET exhibits improved performance than Si TFET because of the lower bandgap [42].

For HTFET and FinFET, an electrical noise model for thermal noise, flicker noise, and shot noise was realized in a differential amplifier with a capacitive load circuit. The circuit shown in **Figure 6** was studied for subthreshold HTFET design to obtain the same range of gain. From the analysis, it evident that the HTFET structure offers to gain twice the gain of FinFET structure. Also, the cut-off frequency is higher in TFET. Also, small-signal amplitudes can be detected by HTFET design. Based on the overall design analysis, it has been found that the proposed device design is more suitable for the applications operating in low-voltage/lowpower [26].

Apart from noise, ambipolar behavior also affects the performance of the device. The comparison of different structures of TFET has been reported by Sathish et al. In TFET structures, heterojunctions have been used to form a source/body junction. By doing so, the tunneling distance can be lowered and the ON current can be increased. It can also be used to control the ambipolar behavior of TFET. Heterojunction TFET characteristics can be determined by using different materials structures [43].

For the fabricated devices at the nanoscale, flicker noise becomes very problematic because flicker noise increases the reducing the device dimensions. The measure of device quality and reliability is done by checking the level of flicker noise. Das et al. presented the analysis of low-frequency flicker noise on dual dielectric pocket HTFET as shown in **Figure 7**. Three different gate-source underlap lengths and different thicknesses were considered. This proposed device exhibits a super steep slope and high current ratio. In the analysis, two different trap distributions (uniform and gaussian) were considered. The study specifies that the ON current of

**Figure 6.** *Representation of noise model implemented at transistor level [26].*

**Figure 7.** *2-D structure of dual dielectric pocket HTEFT [44].*

**Figure 8.** *(a) 2-D structure of novel circular gate TFET (b) and hetero-junction TFET [44].*

the reported HTFET structure is not affected by presence of interface traps as compared to the OFF current [44].

Goswami et al. proposed a new architecture of TFET with a circular gate. The electrical noise analysis was performed for both structures; (a) proposed structure (circular gate), (b) HTFET as shown in **Figure 8** [45]. A comparative analysis for both the structures was done also. The uniform and gaussian trap distributions were simulated and based on the simulation results it can be concluded that structure 'a' shows the lesser impact of noise than structure 'b'. Flicker noise shows an intense effect at low frequency and mid-frequency range. While at high-frequency, diffusion noise effects. Nonetheless, the drain current in structure 'a' is more prone to traps than the drain current in structure 'b'. The cut-off frequency of structure can be improved by using gate-drain underlap and it is well-suited for digital applications.

#### **7. Noise in III-V tunnel FETs**

In the TFET device, during ON state, very low drive current/ON current flows from source to drain. The drive current can be improved by using low bandgap materials like SiGe, InGaAs, InAs. The use of SiGe has been already discussed in the previous section. **Figure 9** shows the schematic diagram of homojunction and heterojunction TFET using III-V materials.

Pandey et al. reported RTN study analysis of HTFET using III-V materials with 20 nm long and 40 nm wide channels. RTN due to the presence of a single charge trap has been modeled by placing the trap charges to pre-defined coordinated mesh. When the electron got captured in a trap, it causes a reduction in the drain current. Also, the analysis of the relative amplitude dependence of RTN on trap location has been performed. Different locations of the trap were considered for the analysis. Firstly, when the trap is present in the channel, from the source towards drain region. Secondly, three different cases can be considered by changing the depth of

**Figure 9.** *Homojunction and heterojunction TFET using III-V materials.*

#### *Noise Analysis in Nanostructured Tunnel Field Devices DOI: http://dx.doi.org/10.5772/intechopen.100633*

the trap like when the trap is (a) present in oxide (b) present in the oxide-channel interface (c) present inside the channel. From the analysis, it has been observed that the relative amplitude of RTNnoise is maximum for case c followed by case b. But the relative RTN amplitude is minimum when the trap is present in gate oxide [13].

Bijesh et al. presented GaAsSb/InGaAs heterojunction TFET using III-V materials. In this work, a high ON current has been achieved at the low drain to source voltage. Also, in the case of InGaAs homojunction, the ON current increases to double the value in heterojunction. Because in heterojunction TFET, reduction in the effective tunneling barrier has been observed. Flicker noise analysis for both homo and heterojunction TFET structure has been performed. The effect of flicker noise on drive current is lower in the case of heterojunction TFET than in homojunction TFET structure. An analytical model to analyze the flicker noise characteristics for both the TFET structure has been developed [46].

Bu et al. developed an analytical model to determine the variation of the electrostatic potential because of the presence of charged trap in the gate oxide of the TFET device. A noise model based on the flow of current through tunneling of carriers in the channel has been proposed. The power spectral density of the TFET device is presented that shows dependency on the frequency and applied gate voltage. It is evident from the analysis that the noise power spectral density of because of the tunneling is more affected by voltage applied at gate terminal than the movement of traps through the channel. The noise observed in the channel is due to the variation in the mobility of traps [47].
