**2. Semiconductor nanowires**

The procedure of the bottom-up growth process of semiconductor NWs can be described as follows (see **Figure 2**); a semiconductor substrate, which could a bulk semiconductor substrate or an epitaxial layer of a semiconductor materials on a glass, for instance, (see **Figure 2**, step 1). A thin continuous layer of few nanometers-thick metal (step 2) evaporated on the surface of the semiconductor epitaxial layer, which segregates in isolated droplets during annealing (step 3). Precursor gas flows in the Chemical Vapor Deposition (CVD) reactor, where semiconductor atoms react at the metal-droplet surfaces, depositing semiconductor vapor atoms into solution within the metal droplets (step 4). The catalyst droplets supersaturate, inducing precipitation of crystalline semiconductor vapor atoms upon the substrate. As precipitation occurs only at the droplet metal (liquid)–semiconductor (solid) interfaces, the semiconductor atoms crystallite in wire structures with diameters comparable to the diameter of the metal droplet (step 5). This growth protocol has been called by Wagner and Ellis as VLS growth after the three coexisting phases: the vaporous precursors (such as Siv), liquid catalyst droplets (such as Aul), and solid silicon substrate (Sis). Notice the possible incorporation of some of the metal atoms (Au) which

#### **Figure 2.**

*A schematic representation shows the sequence of the VLS process in five main steps. The substrate, depicted 1, can be bulk semiconductor materials or a relatively thin film of a semiconductor on a cheap substrate such as glass or polycarbonate (PC) or polymethyl methacrylate (PMMA) sheets; 2: Catalyst thin layer, 3: Catalyst after annealing where it balls up; 4: The sample was placed at the CVD reactor, allowing the precursor gas to flow; temperature reaches the eutectic; three phases coexist; and precipitation begins; and 5: Growth continues forming NWs.*



#### **Table 1.**

*Published experimental research articles of semiconductor nanowires including the techniques and the catalysts.*

catalyzed the growth within the frame of the grown NW (Si-NW), as presented schematically in **Figure 2**.

Semiconductor nanowires have been formed using various methods, as summarized in **Table 1**. Chemical Vapor Deposition (CVD) and Molecular Beam Epitaxy (MBE) have been the main growing systems since the past decade up to recent work for growing various semiconductor nanowires using several catalysts or without catalysts.

#### **3. Epitaxial growth: Silicon nanowires**

The nanowires growth is usually performed in a chemical vapor deposition (CVD) reactor or can be at the Molecular Beam Epitaxy (MBE); see **Figure 3**. The CVD growth mechanism involves the absorption of source material from the vapor phase into a liquid droplet of catalyst above the solid substrate as explained in the original work of Wagner and Ellis, in 1969 [20, 21]. The original proposed VLS mechanism of growing Si-NWs using Au as a catalyst is based on three critical parameters; the presence of the arriving Si **vapor** atoms to the metal droplet in a **liquid** state acting as a preferred position on the **solid** substrate. The detailed growth conditions at the CVD such as the pressure, flow rate, and temperature are placed accordingly. On the other hand, the motivation for using molecular beam epitaxy (MBE) to grow nanowires is that although MBE growth is both complicated and challenging, its high precision and flexibility can give good control over the growth of thin layers and abrupt junctions, which may be an advantage in future nanostructure devices [22].

According to the binary phase diagram of Si and Au, as shown in **Figure 4**, the lowest melting temperature for the Au–Si eutectic is approximately 363°C obtained for a composition of Si and Au. The eutectic is lower than the melting point of Au (1064°C) and Si (1414°C) [21]. Considering that the liquid phase is thermodynamically equilibrated with the solid one, the lowering of the melting point, with the size of the droplet, is given by Eq. (1), as follows [23]:

*Semiconductor Epitaxial Crystal Growth: Silicon Nanowires DOI: http://dx.doi.org/10.5772/intechopen.100935*

#### **Figure 3.**

*Photographs of (a) chemical vapor deposition (CVD) and (b) molecular beam epitaxy (MBE) systems (pictures were taken with permission from nanoscience Center, Cambridge, UK).*

#### **Figure 4.**

*Phase diagram for the Au–Si system. The shaded zone represents the range of temperatures and alloy compositions at which VLS growth might occur [22].*

$$
\delta \mathbf{T} = \mathbf{2} \sigma . \mathbf{T\_0} / (\rho L . r) \tag{1}
$$

where δ*T* is the lowering of the melting point, σ is the interfacial energy,*T***0** is the melting point of the bulk metal, ρis the density of the material,

*L* is the latent heat, and *r* is the radius of the circle of the catalysts. Thus, heating Au film deposited on a Si substrate to a temperature of 363°C results in the formation of liquid Au–Si eutectic. The eutectic is simply a mixture of two elements at such proportions that its melting point is at the lowest possible temperature, much lower than the melting point of either of the two elements that make it up. If these Au–Si melted alloys are placed in an environment containing a gaseous silicon precursor such as silane (SiH4), the precursor molecules decompose into Si and H2 at the outer surface of the metal droplets, thereby supplying additional Si to the Au–Si alloy, and precipitate at the interface between the liquid alloy droplet and the solid substrate.

It has been shown that Si-NWs grow perpendicularly on Si(111), as represented in **Figure 5**.

A variety of derivatives of CVD methods exist, which can be classified by parameters such as the base and operation pressure or the treatment of the precursor. Since Si is known to oxidize easily, it is a key parameter for a successful epitaxial growth of Si-NWs to reduce the oxygen background pressure. In particular, when oxygen-sensitive catalyst materials are used, it turns out to be useful to combine catalyst deposition and nanowire growth in one system, so that growth experiments can be performed without breaking the vacuum in between [24, 25].

#### **Figure 5.**

*Schematic representation of epitaxial growth of Si-NWs (a), where the grown nanowires copy the crystal structure of the substrate, (c) epitaxial grown Si-NWs on Si(111) substrate catalyzed with Al. Detailed growth conditions can be found in Khayyat et al. [24].*

It is often noted in VLS wire growth that the radius of the catalyst droplet exceeds the radius of the nanowire Eq. (2) [22].

$$R = r \sqrt{\mathbf{1} / \left(\mathbf{1} - \left(\sigma\_h \, \prime \, \sigma\_l\right)^2\right)}\tag{2}$$

where *R* is radius of the catalyst droplet, *r* is the radius of the nanowire, σ *<sup>l</sup>* is the surface tension of the liquid catalyst, and σ *ls* is the surface tension of the liquid–catalyst interface. Based on this, one can estimate the growth conditions and deduce the diameters of the catalyst droplet of the resulted growth of NWs with a certain average diameter.

## **4. Si-NWs as building blocks for bottom-up nanotechnology**

Controlling the growth position of an NW is important for fabricating devices, especially when involving a large array of nanowires. The growth reproducibility is critically a key parameter in the progress of implementing nanowires in advance applications.

Free-standing nanowires can be yielded and their position on the wafer can be determined by predefining the position of the seed on the wafer using lithography. There are several research groups working on optimizing the growth of positional Si-NWs [1, 26–28]. Most of the studies till date have used Au due to the convenience of handling that arises from its resistance to oxidation. The current technique is a new method of controlling the position of the grown Si-NWs seeded with oxygen-reactive materials such as Al, which is a standard metal in silicon industrial process line. The technique is based on electron beam lithography for patterning the Si substrate and then forming a Si alloy with Al during a subsequent annealing step. Moreover, it does not require removal of the patterned compound oxide layer [25].

#### **4.1 Nanoscale chemical templating (NCT) technique**

It is an innovative technique that arises as a solution of the issue of the defective planar growth between the grown Si-NWs seeded with Al (or any other chemically active elements). The technique is called Nanoscale Chemical Templating (NCT) of oxygen-reactive elements. Now, what makes NCT an innovative solution? [25].

I.Does not require Al removal for selective growth.

II.Does not require any lithography steps.

III.Multiple application space.

As explained in **Figure 6** (I), the process that does not require Al removal (I-a) shows the patterned SiO2 layer after photolithography, etching, and resist removal. (I-b) After Al deposition and annealing, notice the agglomerated Al:Si feature where it balls up in the openings forming the NW seeds, while the Al in contact with SiO2 has reacted forming Al2O3. (I-c) After NW growth. The NWs are epitaxial and appear as bright spots in the plan view. In the cross sectional view, tapering is visible, due to a thin, non-seeded, Si layer approximately thinner than 1/100 of the length of the nanowire. Notice that a single NW per opening is achieved. (I-c3) and

#### **Figure 6.**

*(I) (a)–(c) schematic illustration of NCT of NWs with corresponding SEM images, cross sectional ((a1), (b1), (c1) and (c3)) and plan views ((a2), (b2), (c2) and (c4)). The scale bars are: (a1) and (b1) 100 nm; (c1) 300 nm; (a2), (b2), and (c2) 1* μ*m; and (c3) and (c4) 20* μ*m. (II) representation of NCT using silica microspheres (a& b) and the corresponding SEM original proof of the concept. (III) schematic representation of the selective growth of AlGaAs for further applications.*

(I-c4) show a larger area containing both a patterned area on the right and an area with no oxide on the left where random growth occurs.

The position control of Si-NWs can be achieved using silica microsphere, as described in 6 (II). The schematic representation of a spinning silica microsphere on the Si substrate, followed by thin-layer evaporation of Al and the subsequent annealing, is shown in (a), where (b) shows the Si-NWs growth. Moreover, paterning III-V semiconductors selectively is considered as one of the possible multiple applications schemes (III).
