**1. Introduction**

The topic of semiconductor nanowires is timely developing research. A legitimate question is then: what makes a material in a nanowire different from a bulk one? The direct answer is the extremely large surface-to-volume ratio. Any application occurs at the surface, such as chemical reactions; it will speed up at a medium of high surface area. Indeed, there are more features of integrating nanowires with the current available technologies (such as PV, AFM, and Raman spectroscopy) [1–5] and as stand-alone applications, such as sensors [6, 7]. Moreover, semiconductor nanowires can be functionalized and tailored in accordance with different requirements. For example, we can dope them with particular elements in the growth stage to change electrical properties or change the growth conditions to vary their shape or size.

There are several techniques of growing semiconductor nanowires. These fabrication methods are based on the semiconductor industrial capabilities, mainly top-down and bottom-up approaches. Photoresist patterning on top of a silicon-oninsulator layer followed by etching silicon and creating vertical silicon columns is explained as a top-down approach. Techniques based on the direct epitaxial growth of nanowires from a seeding material on a substrate are called bottom-up growth techniques, which is the main technique discussed in this chapter (see **Figure 1**).

Studies on silicon nanowires (Si-NWs) started with the pioneer work of Wagner and Ellis in 1965 [1]. The Vapor–Liquid–Solid (VLS) growth method uses metallic droplets or particles as a catalyst to nucleate the growth and absorb gaseous precursors and precipitate them into a solid form to permit crystal growth. The classic example is the VLS growth of Si-NWs on a Si substrate using gold (Au) eutectic droplets. Studying the structural properties of NWs is particularly important so that a reliable procedure of fabrication based on the desired functionality can be designed. Due to the enhanced surface-to-volume ratio in nanowires, their properties may depend critically on their surface condition and geometrical configuration. Even nanowires made of the same material may possess dissimilar properties due to differences in their crystal phase, crystalline size, surface conditions, and aspect ratios, which depend on the synthesis methods and conditions used in their fabrication. Moreover, the temperature of growing NWs is of critical importance, when we integrate them with other electronic devices so that the rest of the components of the electronic circuit do not get damaged at high temperatures. Si-NWs have been thus tried to be grown at low temperatures by utilizing metal catalysts, such as gold (Au) and Aluminum (Al), whose alloys with Si have low eutectic temperatures. Generally speaking, Si-NWs have been shown to provide a promising framework for applying the bottom-up approach (Feynman, 1959) for the design of nanostructures for nanoscience investigations and for potential nanotechnology applications. We are progressing in accordance with the predictions of Moore's Law, which suggests that the number of transistors in a dense integrated circuit doubles every two years [8]. Electronic devices are getting smaller and smaller, and the capabilities of these devices are becoming more leading-edge with the integration with the NWs technology.

#### **Figure 1.**

*Schematic representation shows the original substrate, and the top main approaches of creating nanowires: Bottom-up and top-down approaches. Notice that the building blocks of materials (atoms) are moving toward (deposition) the substrate in the bottom-up process, while atoms are moving away (etching) from the substrate in the top-down mechanism.*
