**8. Impact of noise in TFET based circuit and memory design**

In the processors, SRAM memory cell have been broadly used as data caches and these memory cells are the most significant digital building blocks. Fan et al. widely reviewed the effect of single-trap-induced RTN on TFET, and FinFET. The effect of noise on BTBT dominated current conduction in TFET and thermionic based current conduction has been presented in both device and circuit level. The trap location has an intensive effect and that effect varies with applied bias variation and type of trap. The worst-case analysis of different parameters for RTN noise has been investigated for TFET based 6 T/8 T SRAM cells [48]. For different trap locations A, B, C, A', B<sup>0</sup> the analysis of TFET device has been performed. **Figure 10** demonstrates the diagram of reverse-biased TFET with a single charge trap and having asymmetric source and drain dopant concentrations.

**Figure 10.** *Potential contour by charge trap [48].*

#### *21st Century Nanostructured Materials – Physics, Chemistry, Classification, and Emerging …*

#### **Figure 11.** *TFET electron density profile for two different voltages [50].*

S.H. Fani et al. presented a new low-power TFET 8 T-SRAM cell with an improved noise margin. The stability of the 8 T-SRAM cell was improved by using supply feedback. The proposed structure exhibits 33% in reading noise margin and 26% in write margin as compared to conventional 6 T SRAM cell for the supply voltage of 0.3 V. The area of the proposed SRAM is larger than the existing one but the features like stability and high performance at very low voltage supply make it useful. The use of the TFET device has limited the working of SRAM cells as it is a unidirectional device but this issue has been resolved by using transistors (n-type and p-type) placed parallelly and the use of one bit-line [49].

The investigation of the effect of RTN noise present in TFET-based 8 T SRAM cell was done by Fan et al. To account the effect of negatively charged trap, the atomistic 3D TCAD simulations were performed for the analysis of TFET-based SRAM. From the analysis, it has been observed that if the trap is present near the tunneling junction, fluctuation in drain current has been observed. The RTN causes 16% additional variation for 8 T SRAM circuit configuration [50]. The electron current density profile for gate voltage values of 0 V and 0.2 V has been shown in **Figure 11**. An increase in gate voltage increases the electron current density.

Luong et al. fabricated half SRAM (HSRAM) cells to examine the capability of TFETs for 6 T-SRAM for the first time. This reported structure has been strained with Si nanowire. The proposed TFET structure does not work up to the mark even when the ambipolar behavior has not been included. Also, analysis of the proposed structure has restricted the static figure of merit [51].

Pandey et al. investigated the effect of a single charge trap RTN in HTFET-based SRAM. This study focused on the analysis of Schmitt trigger mechanism-based variation tolerant 10 T SRAM. A comparison of Si-FinFET and HTFET in terms of iso-area SRAM cell configurations has been done. It has been clear from the analysis that HTFET based SRAM cells show very good performance even in the presence of RTN. For the applied voltage of 0.2 V, the proposed structure offers 15% more improvement as compared to Si-FinFET. Also, the HTFET ST SRAM structure shows less delay in a read operation and consumes less power [52].

The performance of MOSFET devices degrades on scaling down the dimensions. All the issues can be solved using TFET structures as TFET devices offer low leakage current and steeper SS. Nonetheless, TFETs are ambipolar and produce low ON current. However, this behavior can be overcome by using increasing the doping concentration. The main challenges in TFETs are to achieve high ON current, low OFF current, and low average SS. By choosing an accurate predictive model, proper choice of materials, and dimensions of the device, these challenges can be overcome.

### **9. Conclusion**

Noise is one of the important parameters in terms of reliability. This review reported the impact of noise in Tunnel FET devices to understand the reliability issues. The detail discussion has been done for the random telegraph noise, thermal *Noise Analysis in Nanostructured Tunnel Field Devices DOI: http://dx.doi.org/10.5772/intechopen.100633*

noise, flicker noise, and shot noise for Si/Ge TFET and III-V TFETs. Recent research work for both low frequency as well high frequency noise for different TFET device design has been discussed in details. The effect of noise for memory and circuit based on Tunnel FET devices as also been discussed. The effect of noise on BTBT dominated current conduction in TFET and thermionic based current conduction has been presented in both device and circuit level. The analytical models for noise analysis of different TFETs structures has also been reported which is required for circuit implementation and memory design.
