7. Steps for the realization of the structure and its electronics

We start by the voltage "doubler". These electronics are produced using CMOS technology with 8 ion implantations on an S.O.I wafer with an intrinsic silicon layer above the oxide:


Once this electronics is done, we are interested in the realization of the structure of CASIMIR with the following technology proposal:

9.engrave the S.O.I. silicon to the oxide to define the location of the Casimir structures (Figure 56)

Perspective Chapter: Device, Electronic,Technology for a M.E.M.S. Which Allow… DOI: http://dx.doi.org/10.5772/intechopen.105197

Figure 56. Etching of S.O.I silicon.

Figure 57. Engraving of the protective metal rear face of the S.O.I. silicon.


Figure 58.

Deposition and etching of the piezoelectric layer e 61 deposition and etching of the piezoelectric layer.

Figure 59. Metal deposit, metal engraving etching of the piezoelectric layer.

#### Figure 60.

View of the Casimir device on the rear face, engraving on the rear face of the structures.

Figure 61. Adjusted growth of metal oxide under the electronic control, front view of the Casimir device.


In the case where the 2 metal electrodes of Casimir which are separated by a very weak interface, of the order of 200 A°, adhere to one another, then these two surfaces can be separated by the application of an electrical voltage on the electrodes on the other side of the piezoelectric bridge!

In order to obtain a current peak greater in intensity and duration, the Casimir cells can be positioned in a series and parallel network at the 2 terminals of a single inductance. For example, 20 Casimir cells can be placed in parallel and 10 in series.

Circuit 1: parallel MOSPE and MOSNE ; see Fig. 6.

Circuit 2: serial MOSPD and MOSND ; see Fig. 6.

Perspective Chapter: Device, Electronic,Technology for a M.E.M.S. Which Allow… DOI: http://dx.doi.org/10.5772/intechopen.105197
