**5. Light-weight IEC 61850 implementation of the developed control algorithm based hardware-in-the-loop**

In order to test the developed light-weight IEDs based on the HIL simulations, the Substation Configuration Description (SCD) file was developed and further adapted into two different hardware, namely to the BeagleBone Black (BBB) and the Field Programmable Gate Array (FPGA). The flow steps of the developed C code start with the designed IEC 61850 IEDs based on the defined data attributes, data objects, LNs, LDs as well as it includes the operating functions, and the underlying communication protocols.

A "lightweight" IED need to implement the IEC 61850–8-1 (mapping the IED data to GOOSE) for the horizontal communication by using the open source library "libiec61850". Furthermore, the designed IEDs generated by this process will compliance with the IEC 61850 detention and agree the interoperability concept that offered by the IEC 61850 standard. As well as the IED is flexible, scalable and can be updated based on the valid SCD file. Within the open source library "libiec61850" the overall C code project files can be generated automatically based on define internal data model. This approach will reduce the research and development runtime and maximize the performance and facilitates the use of relatively low-cost embedded devices and FPGA.

**Figure 2** depicts the instruction designing procedure for the "lightweight" IEDs that presented in this study. Within the first step SCD (.icd) file need to be designed based on the defined energy system aspects that includes the data attributes (DA) types, data object (DO), logical node (LN), logical devices LDs as well as communication instances of the model.

At the second step, and from the predesigned SCD file that include all the IEC 61850 data, a C code is automatically generated by the "libiec61850 model generator". This generated code is the representation of the model and their communication instances that tailored to the designed model. At this point the "model generator" attempts to convert and mapped each type of IEC 61850 data model into a C data structure. From this process a hierarchy C data structure file will achieved and collected into the project folder.

The third step was to define the parameters that are needed to be subscribed. Then to compile the design project file (or application file) to generate the execution file for running the project in the hardware under test.

The fourth step was about extracting the defined parameters (in this case the status of the main supply) from the subscribing GOOSE message from the model. Next step describes the execution of the control algorithm in the hardware and based on the result, the new status value need to be send over the communication network from the controller via IEC 61850 GOOSE protocol. On the other side the target were the simulation model is running is able to subscribe to the GOOSE message and extract the useful data to be used within the running model in real-time.

Lastly the designed project need to be tested. For cost reduction and simplicity advanced reduced instruction set computer (RISC) Machines (ARM) processor-based microcontroller BeagleBoneBlack (BBB) as well as by the ARM processor-based SoC FPGA are used. Both are compatible with C and C++ compilers.
