**4. Logic implementation and computational operations by 2M1M memory cell**

Composite memory cells can be applied to implement digital logics. In addition to its memory application, the proposed memory cell is capable of implementing logic which makes it capable for in-memory computing applications. Here, in this section we are assessing the logic implementation of the proposed architecture with 2M1M cells.

### **4.1 Logic gates with 2M1M switch**

From switching point of view, this circuit is a three state switch as 'ON', 'OFF' and 'No-Change'. Interestingly, this switch can also be used as logic gates. By setting the initial memristance value of the output memristor to *R*on or *R*off, final memristance state of memristor XC, respectively, AND or OR logic gate operations are developed. Further, by changing the polarity of the output memristor (XC) one can make NAND and NOR gates in a similar way. Therefore, the 2M1M array can develop two different logic schemes based on the polarity of memristor XC. First, include AND and OR gates and by changing the polarity of XC the array can develop NAND and NOR gates. The logic is based on the resistance of device and not the voltage. This will make this logic to enable in-memory compute logic family as the data will store within the memory array after finishing the operation.

The input voltage pulses with amplitude +*V* and �*V* are applied as logic 1 and 0 into the rows a1 and b1. Other unselected rows will be floated and the column c1 is grounded to shape a 2M1M cell 11 as a logic gate. Other unselected columns need to be floated to inactive the rest of the 2M1M cells in the corresponding row. As an example, the AND gate can be implemented by a 2M1M switch over the 2M1M array by applying the appropriate voltages. This gate is comprised of two access devices XA and XB which are connected in parallel with different polarities to node *M*. The output device XC is connected between node M and bit-line of the array by a positive polarity. The input voltages should be applied to a1 and b1 lines as *V*<sup>A</sup> and


#### **Table 4.** *Truth table of the proposed memristor logic gates.*


**Table 5.**

*Comparison of proposed 2M1M logic gates with [15, 27].*

*V*B. Also, *R*<sup>C</sup> >> *R*A, *R*<sup>B</sup> and the resistance of *R*<sup>C</sup> will specify the output of the logic. The logic can be described for different input combinations by considering the Eqs. (1)–(5).

The truth table of different 2M1M logic gates has been in presented in **Table 4**, by showing different input combination voltages, output voltage and resistance state of the output device. Different 2M1M logic cells, their implementations on memristor crossbar array and the simulation results corresponding to each AND, NAND, OR, and NOR logic gates by using 2M1M cells for different input combinations have been displayed in **Figure 7**. In **Table 5**, the proposed 2M1M logic gates have been compared in terms of number of with IMPLY logic [27] and 4M1M [15]. It has been shown that the proposed logic requires only one computational step to implement in-memory logic for AND, NAND, OR, and NOR gates. Also, the number of required devices to implement all of these logic gates are 3 devices included in a 2M1M cell structure.

Sneak path current is considered as one of the important challenges against practical application of memristor crossbars. During reading operation the sneak path currents through neighbor cells can affect readout value of the target cell. To eliminate or reduce the sneak path in the crossbar array several methods have been proposed by researchers. In general, proposed methods can be divided into two categories. In the first approach [33–36], researchers focus on device level structure of the memristor or read process in the crossbar to make it more resilient against this effect. Among these methods is the way provided in [33] in which read operation is done by an algorithm in several stages. This method improves the sneak path problem but increases read time and require additional circuit to realize the read algorithm stages. Another approach relies on memristive devices with inherent nonlinear structure such as [34, 35] in which a three-terminal memristor device is proposed to solve this problem. In another approach as presented in [36] to eliminate sneak path currents separate columns are considered for each element in the crossbar architecture. That increases cell area and therefore reduces the memory density. In the second approach, to solve the problem of sneak path currents, it is suggested to add additional switches to each memory cell in the crossbar architecture to separate reading path of the target cell from the other unwanted paths. There are several suggestions in this approach, but the most popular structure is 1T1M (one transistor for one memristor) [14]. This structure uses a transistor to separate each cell from other cells during read operation. In this way, added transistor is the gating element of the cell. This method has problems due to the scalability considerations of the CMOS-memristor structure [13]. In [23] diodes,

*Development of Compute-in-Memory Memristive Crossbar Architecture with… DOI: http://dx.doi.org/10.5772/intechopen.99634*

instead of transistors, have been suggested to reduce sneak path. There are difficulties with this approach as well due to diode behavior. In another approach [28], back-to-back memristors are proposed to overcome the problem of sneak path current in which always one of the memristors is in *R*off state and the other one is *R*on. In this way, equivalent memristance is always greater than *R*off which can reduce the sneak path effect. In [15] a memristor based switch is suggested to solve the problem of sneak path. In this method at least one of the input memristors is always in state *R*on, which connects target cell to other cells in the row through a low resistive network. In this structure, as shown in **Figure 9**, during write process, there is a detour current path through MS-MP and MT-MP, in all parallel branches in the crossbar structure; witch can considerably increase the writing current and power consumption.

In this study, effect of sneak path can be easily reduced using proposed gating mechanism created by XA and XB memristors in the cell. By changing state of these memristors to *R*off, memristor XC, which keeps the saved value ('0' or '1') of the memory cell, can be isolated from rest of the network. As discussed before, in the second and third rows of the truth table switch goes to No-Change state and XC keeps its sate untouched, where both XA and XB memristors become either *R*off or *R*on. Therefore, if in the crossbar array structure, we apply *V* and +*V* to ai and bi lines of the row respectively, memristors XA and XB of all the cells in the row will to *R*off state, which is a high impedance, without any change in their XC memristance. So unlike cells provided in [15] there is no resistance of *R*on between the selected node and the other nodes of the circuit. In fact, high impedance of the XA and XB memristors isolate XC of all the cells in the crossbar from each other.

With this approach equivalent circuit of the neighboring cells in a row is as shown in **Figure 9**. Interestingly, target cell (first cell from left) sees an equivalent resistor of the network which is almost independent from stored values (in terms of *R*on or *R*off) in other cells. This means if *R*float >> *R*off then effect of *R*<sup>c</sup> state is negligible on *I*read current. Simulation results are presented in **Table 6**. As it can be seen this method is far better than [15, 24]. In comparison with [31] sneak path current in this work is higher but please note that in [31] there are two transistors for each memory cell but our cell is transistor-less.

#### **Figure 9.**

*Sneak path current in 4M1M cell [15] and the proposed 2M1M crossbar memory in a read operation. (a) 4M1M [15] sneak path currents in read operation. (b) Sneak path current in 2M1M crossbar during read operation. Figure reprinted by [9].*


#### **Table 6.**

*Comparison of sneak current effect of the proposed architecture with other architectures.*


**Table 7.**

*Comparisons of density and energy consumption with previous works.*

By providing the structure and strategies for array-based 1S1R [16–22], many of the structures have offered while having high density 4*F*<sup>2</sup> , very small sneak paths current, very low power consumption and high read margin that is very promising. Compared with 2M1M structure, can be said that 1S1R based structures has been created in series connection memory element and selector in terms of manufacturing technology because are of the two different types perhaps compared with 2M1M structure which is a memristor uniform structure be more complexity. And in the 2M1M structure used of memristor, that is a memory and a computing element. The aim is to implementation the logic and computing capabilities for future applications of this structure in memory which can help to achieve a beyond classical von Neumann architecture. It hopes that by development and progression of 2M1M, the valuable feature in 1S1R structure is achieved for a higher density and removes sneak paths. Approximated device density and power consumption of the proposed architecture is compared with previous works in **Table 7**. As it is attainable form this table, due to lower number of memristors per memory cell, proposed architecture offers higher density compared with previous works. In terms of power consumption, since authors did not find a clear explanation regarding details of previous studies for their power calculations, power consumption of the cells in various operations are presented and compared in details.
