**2.1 2M1M switch circuit**

The 2M1M three state switch [9] which functions in ON, OFF, and NC are shown in **Figure 1**. As it can be seen, the proposed memory cell comprises of three memristor devices XA, XB and XC. XA and XB devices are the access devices and they isolate the target device XC which stores the information. There are three terminals A, B, and C in this structure in which A and B are considered as input terminals and Va and Vb (as input voltages of '*V*' or '+*V*') should be applied to terminals A and B respectively. Operation of the circuit, regarding *V*<sup>a</sup> and *V*<sup>b</sup> as input voltages and *V*<sup>M</sup> as its output can be explained as follows. The input voltage (+*V*) for logic '1' and the input voltage (*V*) for the logic '0' are applied to the XA and XB memristors (|*V*| > |*V*th|). The voltage *V*<sup>M</sup> on common node of memristors represents output of the circuit while memristor XC maintains this value in form of memristance. The truth table of this circuit is shown in **Table 1**.

#### **Figure 1.**

*Schematic of the proposed memory cell. (a) General circuit of memory cell. (b) Configuration for switch circuit mode. Figure reprinted by [9].*


**Table 1.** *Truth table for the proposed switch circuit.*

$$\begin{aligned} \frac{(V\_M - V\_a)}{R\_a} + \frac{(V\_M - V\_b)}{R\_b} + \frac{V\_M}{R\_c} &= \mathbf{0} \\ \rightarrow V\_M \left(\frac{\mathbf{1}}{R\_a} + \frac{\mathbf{1}}{R\_b} + \frac{\mathbf{1}}{R\_c}\right) &= \frac{V\_a}{R\_a} + \frac{V\_b}{R\_b} \end{aligned} \tag{1}$$

and providing *R*a, *R*<sup>b</sup> < < *R*<sup>c</sup> we can approximate *V*<sup>M</sup> as:

$$V\_M = \frac{R\_b}{R\_a + R\_b} V\_a + \frac{R\_a}{R\_a + R\_b} V\_b \tag{2}$$

When both inputs are '0' (�*V*) according to the polarity of memristors, since a negative voltage is applied across memristor XA and a positive voltage across memristor XB, so their memristance, regardless of their initial states, will change to Roff and Ron, respectively. Therefore, according to Kirchhoff's law and also considering the initial state of the memristor XC, as *R*<sup>C</sup> >> *R*A, *R*<sup>B</sup> (memristance of XA and XB), the voltage in common node of memristors is: *V*<sup>M</sup> = �*V*. This will set memristance of XC to *R*off, which is logical zero:

$$\begin{aligned} V\_a &= V\_b = -V\\ V\_M &= \frac{R\_a + R\_b}{R\_a + R\_b} \cdot (-V) = (-V) \approx \text{Logical } \mathbf{0} \end{aligned} \tag{3}$$

For logic 1, according to the fourth row of the **Table 1**, when both inputs are in the same value of +*V*, similarly, based on the polarity and direction of memristors, the memristor XA is set to *R*on and memristor XB becomes *R*off. Therefore, the voltage on the output node (M) is approximately +*V* which will change the memristance of the output memristor, XC, to *R*on representing logical one:

*Development of Compute-in-Memory Memristive Crossbar Architecture with… DOI: http://dx.doi.org/10.5772/intechopen.99634*

$$\begin{aligned} V\_a &= V\_b = V\\ V\_M &= \frac{R\_a + R\_b}{R\_a + R\_b} \cdot V = V \approx \text{Logical1} \end{aligned} \tag{4}$$

Otherwise, if the value of input voltages is different as (+*V*) and (�*V*), both input memristors have the same value of either *R*on or *R*off according to the applied voltage and their polarity. This results in a zero voltage on common node. Since *V*<sup>c</sup> = 0, in this case memristance of XC does not change:

$$\begin{aligned} V\_a &= -V\_b = V\\ V\_M &= \frac{R\_{on}}{R\_{on} + R\_{on}} \cdot V + \frac{R\_{on}}{R\_{on} + R\_{on}} \cdot (-V) = \mathbf{0} \end{aligned} \tag{5}$$

or similarly:

$$\begin{aligned} V\_a &= -V\_b = (-V) \\ V\_M &= \frac{R\_{\theta \overline{f}}}{R\_{\theta \overline{f}} + R\_{\theta \overline{f}}} \cdot (-V) + \frac{R\_{\theta \overline{f}}}{R\_{\theta \overline{f}} + R\_{\theta \overline{f}}} \cdot V = 0 \end{aligned} \tag{6}$$

This state is called a NO-Change state. To have a timing analysis of switches operation, according to [15]:

$$\frac{d\mathcal{R}(t)}{dt} = -k \cdot i(t) = -k \cdot \frac{V}{R(t)}\tag{7}$$

$$k = \mu . \Delta R \cdot R\_{on} / D^2 \tag{8}$$

$$
\Delta R = R\_{q\overline{f}} - R\_{on} \tag{9}
$$

Because in the fourth combination of the truth table of memristor based switch (**Table 1**), memristor XA is parallel with memristor XB then *V*<sup>a</sup> = *V*b. Therefore:

$$V\_a = \frac{R(t) \cdot dR(t)}{-k \cdot d(t)}\tag{10}$$

By integrating (8) and also assuming that *ϕ*<sup>0</sup> ¼ 0, *ϕ*ð Þ*t* is given by

$$
\int Va = \int \frac{R(t) \cdot dR(t)}{-k \cdot d(t)} = \int \frac{d\phi}{dt} \tag{11}
$$

$$\left|R\_a{}^2(t) - R\_{ai}{}^2 = -\mathcal{Q}k\_a\phi(t)\right.\tag{12}$$

$$\phi(t) = \frac{\left(R\_a^{\;2}(t) - R\_{ai}^{\;2}\right)}{-2k\_d} \tag{13}$$

and also by supposing the initial state of memristor XA is *R*off and its final state is *R*on, the required flux across the memristor XA is

$$\phi(t) = \frac{\left(\mathcal{R}\_{on}{}^2 - \mathcal{R}\_{off}{}^2\right)}{-2k\_a} \tag{14}$$

Thus, the required time for change state of memristor XA and XB is given by:

$$
\Delta \phi\_a = V\_a T\_1 \tag{15}
$$

*Memristor - An Emerging Device for Post-Moore's Computing and Applications*

$$\begin{aligned} T\_1 &= \frac{\left(R\_{on} + R\_{off}\right) \cdot D^2}{-2V\_d \mu\_v R\_{on}} \\ T\_1 &= T\_2 \end{aligned} \tag{16}$$

In memristor XC the required time for the change of state is:

$$T\_3 = \frac{\left(R\_{on}^{\prime} + R\_{off}^{\prime}\right) \cdot D^2}{-2V\_C \mu\_v^{\prime} R\_{on}^{\prime}}\tag{17}$$

Therefore, the total time to change the cell state,*T*t, is given by:

$$\begin{aligned} T\_t &= T\_1 + T\_3\\ T\_t &= \frac{\left(R\_{\text{eff}}\,^2 - R\_{on}\,^2\right)}{-2k\_a V\_a} + \frac{\left(R\_{on}' + R\_{\text{eff}}'\right) \cdot D^2}{-2V\_C \mu\_v' R\_{on}'} \end{aligned} \tag{18}$$

#### *2.1.1 Simulation result for 2M1M switch circuit*

This is in general agreement with the simulation results as presented in follow, Despite several memristor SPICE models which are presented in [28, 29], the simulation results are performed using Biolek model presented in [30]. This model is selected due to the fact that, it can be utilized in mathematical analysis for power and delay estimation besides its validity to characterize the memristor switching behavior. PSPICE software has been utilized to perform the simulations. The simulations are carried out by using the parameters in **Table 2**, and for a fair comparison, these parameters are similar with [15] to evaluate functionality of the design.

Different combinations of inputs which are applied to the switch are shown in **Figure 2**. As it can be seen the simulations results are in agreement with the truth table of **Table 1**. Here the voltage is applied and output logics is represented by memristance of the XC. Delay or settling times for this switch is defined by the time which XC memristance reaches to its final value. According to the simulation results, this time is 1.11 ns which is also in agreement with theoretical calculations.
