**2.2 Write and read operations**

For the write operation, the memory cell should work based on the first and forth rows of **Table 1**, respectively for writing '0' and '1', as descried in details in subsection 2.1. For read operation, unlike previous works, these cells do not need any additional wiring or complicated sense circuitry. This is because in this circuit


**Table 2.** *Simulation parameters for 2M1M memory architecture.* *Development of Compute-in-Memory Memristive Crossbar Architecture with… DOI: http://dx.doi.org/10.5772/intechopen.99634*

#### **Figure 2.**

*Memristor switch circuit simulation results for different cases. In each subfigure, upper figure displays the inputs and common node voltages while the below figure displays the output device resistance state. (a)* a *= 0,* B *= 0. (b)* a *= 0,* B *= 1. (c)* a *= 1,* B *= 0. (d)* a *= 1,* B *= 1. Figure reprinted by [9].*

#### **Figure 3.**

*(a) Write and (b) read circuit configurations of the proposed memory cell. (c) 2M1M Memristor-based crossbar architecture. Figure reprinted by [9].*

memristor change inertia, as shown in **Figure 3**, is exploited. In general, the READ operation is done by floating node B and applying READ signal *V*<sup>R</sup> to node C. Then, a sense amplifier (SA) is sensed the current from node A of the memory cell. In other words, in this technique a read signal is applied to the memristor which does not change the memristance, either because of its high frequency (*f* > *f*th) or/and because of its low voltage (*V* < *V*th).

In read process method, a pulse *V*R with appropriate amplitude and small duration is applied to the circuit as "read signal". A sense amplifier then measures value of the propagated signal on port A of the switch. Width and amplitude of this pulse (or spike) should be chosen in a way to do not affect memristors'state during read process. As mentioned before in high frequencies memristor operates like a pure resistive element. If we connect A and B ports of the proposed circuit to the ground, and apply to the other end of the memristor XC (port C), a read spike with amplitude voltage of 2 V, as shown in **Figure 3b**, the output voltage can be read at node VM as:

$$V\_M = \frac{\left(R\_{on} || R\_{off}\right)}{\left(R\_{on} || R\_{off}\right) + R\_c} \cdot 2V \cong \frac{R\_{on}}{R\_{on} + R\_c} \cdot 2V\tag{19}$$

which in terms of logic vales can be described as:

$$\begin{aligned} \text{if } &: R\_c = R\_{on} \to V\_M = V = \text{logical} \quad \mathbf{1} \\ \text{if } &: R\_c = R\_{off} \to V\_M \cong \mathbf{0} = \text{logical} \quad \mathbf{0} \end{aligned} \tag{20}$$

With this technique we can increase reading speed and reduce power consumption. In addition, if we read the output value from port A instead of node M, this read method does not require any additional wiring to access node M. This considerably reduces fabrication and wiring complexity of the proposed crossbar structure.
