**3. 2M1M Memristor crossbar architecture**

In crossbar architecture the 2M1M memory cell can be used effectively as shown in **Figure 3c**. While, there is no need CMOS transistors for each cell within cross bar fabric in this architecture. As it can be seen in **Figure 3c**, the similar nodes of memory cells in the crossbar structure are connected to each other in the horizontal rows nodes Ai and Bi are of the cells are connected to each other separately while in vertical columns modes Ci are connected to each other. The desired reading or writing operation are performed by applying appropriate voltages in suitable rows and columns to activate a cell and disable others.

#### **3.1 Write operation in the crossbar**

For write operation in the crossbar architecture, like a single memory cell, appropriate input values need to be applied to the memory cell based on **Table 1**. This means that, both applied voltages *V*<sup>a</sup> and *V*<sup>b</sup> should be similar, either amount of '+*V*' or '�*V*' to write logical '1' or to write logical '0' respectively. Otherwise, the other states in truth table, the switch is in the No-Change state. This scheme is easily applicable to the crossbar structure in the same way as a single cell using connected cell port (ai, bi and ci). It should be considered that when read or write signal are applied, cells should be completely isolated from the target cell. When writing in a cell (or a number of associated cells as a word), the other cells should have maintained their saved vales. For more explanation for write operation, as an example. Considering cell 22 as a target cell to write '0' ('1') in **Figure 4**. In this case, the same voltages �*V* (similarly +*V* for '1') should be applied to both memristors XA and XB and node C is connected to GND. In this situation, in terms of applied voltages

#### **Figure 4.**

*(a) Write configuration in 3* � *3 2M1M crossbar memory and the hazardous zones are displayed. Z1 zone contains target cell 22 and highlighted by green. (b) Resistive equivalent circuit of zone Z2 in the proposed 3* � *3 2M1M crossbar memory. The equivalent resistor circuit of the target cell 22 is highlighted by green. Figure reprinted by [9].*

*Development of Compute-in-Memory Memristive Crossbar Architecture with… DOI: http://dx.doi.org/10.5772/intechopen.99634*

combination, four different zones are recognizable in the crossbar structure, as shown in **Figure 4**. As it can be seen only the target cell is located in the first area, Z1. The second area is Z2, where all cells have the same voltages as target cell on their ai and bi nodes. In the third area, Z3, cells have the voltage on their node C, which is the same as the target cell 22. In the fourth zone, Z4, there is no input in common with cell 22. In the Z1 to write '0' ('1') into the cell 22 voltage *V* (+*V*) is applied to rows *V*b2 and *V*a2 where the column *V*c2 is connected to GND.

As can be seen in the **Figure 4**, Z2 is the hazardous zone because in this area same voltages as the target cell (*V* or +*V*) are applied to the *V*a2 and *V*b2 ports of the cells. It can cause an unwanted writing and changing the state of the memristors that are not supposed to change. To deal with this issue, C nodes of the neighbor cells in zone Z2 are floated or in practice connected to a high impedance open circuit (the columns *V*c1 and *V*c3 in **Figure 4**). Since the columns c1 and c2 are floated, we consider a resistance *R*Float for each of these columns and this resistance is connected to the non-bar side of the XC device in each of 21 and 23 2M1M memory cells. The bar side of XC device is connected to the common node between XA and XB devices. Then, the equivalent resistor-based circuit for cell 21 has two serially connected resistors *R*a21 and *R*b21 which are connected to rows a2 and b2 and they are memristances of XA and XB devices in cell 21, respectively. The common node of XA and XB is connected to a *R*c21 resistor which is a memristance of Xc device in cell 21. Therefore, resistance of the float column *R*Float will be in series with *R*c21 resistor (this is true for cell 23). If the float resistance terminals were connected to both terminals of XC device, then we could consider *R*Float was parallel with *R*c21 while here only the non-bar side of XC device is connected to the floated column c1.

Resistor equivalent circuit of this zone is depicted in **Figure 4b**. This floated port connection reduces current through XC memristor of the unselected cells (≈ 0) which keeps the stored values of the cells untouched. The rest of the rows and columns in the cross-bar structure are connected to ground. Thus, points A, B and C of cells that are in zones Z3 and Z4 are either floating or connected to GND. the logical state of these cells therefore do not change during write operation. Although, maybe one of the two memristor XA and XB is sufficient to perform write operations and by help one of them could to done correctly write operation but as mentioned, this structure is designed to be based on a three-state switch ON, OFF and NO Change. The second case is used to high impedance operation for memristors without changing of output memristor in practice reading that through this can reduce the sneak paths current. In addition, one of the applications of these cells has been mentioned is the implementation of logic circuits which is explained in the Section 4. Please note that in this structure cells in the same column are almost independent and can be written or read simultaneously. This makes it possible to have a parallel read/write process on these cells for higher rate memory access operations or combine a number of them forming data "word" rather than collections of single bits.

In the write operation as can be seen in **Figure 4a**, the memory cells 21 and 23 are in zone 2 and they are the neighboring cells of the target cell for write operation. The equivalent resistor-based circuit of these cells are displayed in **Figure 4b**. Write operation of the memory cell in 33 2M1M crossbar array is simulated in **Figure 5a** and **b**. This memory cell is functioning even by having a time difference between the applied voltage input *V*<sup>a</sup> and *V*b. To test the proposed memory cell for this special case, two asynchronous input voltages are applied to the memory cell and the simulation results prove its functionality (**Figure 5c**).

#### **3.2 Read operation in the crossbar**

Regarding read operation, there are four zones in the crossbar as described in previous section. During read operation, as shown in **Figure 6a**, by applying voltage

#### **Figure 5.**

*Writing in target cell with different neighbor cell's stored value. (a) Write 1 in target cell. (b) Write 0 in target cell. (c) Write operation when two asynchronous input voltages are applied to the target cell with the time difference. Figure reprinted by [9].*

#### **Figure 6.**

*Read configuration in 33 2M1M crossbar memory and the hazardous zones are displayed. (a) Z1 which contains target cell 22 is highlighted by green. Equivalent resistive circuit for hazardous zone for read operation. Target cell for read operation is highlighted by orange. (b) Resistive circuit for hazardous zone in 33 2M1M crossbar memory. (c) Equivalent resistive circuit by considering n neighbor cells. Figure reprinted by [9].*

VR to node C and stored bit in XC can be read as a voltage from node A. Suppose that we want to read from cell 22. The read operation must be performed in 2 stages; in the first stage, memristors XA, XB of the Z2 memory cells are changed to high impedance (*R*off) to partially isolate neighbor cells in this zone from applied read spike which can be done by applying voltages *V* and +*V*, according to truth table of **Table 1**, to lines *V*<sup>a</sup> and *V*<sup>b</sup> of the cells in the zone respectively. At second stage the read signal is applied to port C of the target cell and voltage of port A of the cell is read. This stage must be performed by floating row *V*b2, applying voltage *V*<sup>C</sup> to column *V*c2, reading (measuring) the voltage on node A using a sense amplifier. The important point at this stage is considering appropriate signal as read signal. It is very important that applied read pulse be strong enough to induce a readable voltage at A line of the row. And also this signal should not affect memristance values of the memristors in the target cell or the neighbors. Here a spike shaped narrow pulse is used as read signal (*V*C).

Another consideration which is so important in this crossbar architecture is effect of neighbor cells in the output readout value. In this case the circuit can be assumed as a resistive network and areas involved in this operation are Z1, Z2 that *Development of Compute-in-Memory Memristive Crossbar Architecture with… DOI: http://dx.doi.org/10.5772/intechopen.99634*

can be seen in **Figure 6**. Sneak path current is considered as one of the most important issues in memristor crossbar memories. Here, XA and XB of the neighbor cells to "gate" effect of the XC memristance of the neighbors from read signal are used. By changing memristance of XA and XB memristors of the neighbors to *R*off, as shown in **Figure 6b**, the target cell will be in parallel connection with its neighbors which are gated form ai line by 2*R*off memristance. Since all cells in these areas, except cell 22, have a floating (*R*float) resistance connected to the node C, each neighbor cell can be considered as a 2Roff resistors in parallel with cell 22. The value of these parallel resistances is equivalent to (2/*n*) � *R*off (*n* = total number of columns per row). Accordingly, equivalent resistance of the neighbor cells from ai line is almost independent from their XC memristance, which represents stored value in the cell. This technique considerably reduces sneak path effect and its negative effect on cells' readout process. Using equivalent circuit of **Figure 6c**, the readout voltage and equivalent neighbor cells resistance can be calculated as:

$$\left| V\_a = \frac{R\_{sense}}{\left( \left( \mathbf{1} + \frac{2}{n} \right) R\_{\partial f} \right) \left| R\_{\partial f} \right\rangle + R\_c + R\_{sense}}. \right. \\ \tag{21}$$

$$(1 + \frac{2}{n})R\_{\mathcal{off}}) \vert R\_{\mathcal{off}} \rangle \cong \frac{R\_{\mathcal{off}}}{2} \tag{22}$$

by selecting of *R*sense = *R*off,

#### **Figure 7.**

*2M1M array logic schematics and simulation results for AND, NAND, OR, and NOR. (a) AND logic gate for 2M1M switch. (b) NAND logic gate for 2M1M switch. (c) OR logic gate for 2M1M switch. (d) NOR logic gate for 2M1M switch.*

$$\begin{aligned} V\_{a} &= \frac{R\_{\text{eff}}}{\frac{R\_{\text{off}}}{2} + R\_{c} + R\_{\text{off}}} \cdot V\_{c} \\ \text{if } &: R\_{c} = R\_{on} \Rightarrow V\_{a} = \frac{R\_{\text{off}}}{\frac{R\_{\text{off}}}{2} + R\_{on} + R\_{\text{off}}} \cdot V\_{c} \approx \text{Logical }\,\,\,\text{'1'} \\ \text{if } &: R\_{c} = R\_{\text{off}} \Rightarrow V\_{a} = \frac{R\_{\text{off}}}{\frac{R\_{\text{off}}}{2} + R\_{\text{off}} + R\_{\text{off}}} \cdot V\_{c} \approx \text{Logical }\,\,\,\,\text{'0'} \end{aligned} \tag{23}$$

The second voltage *V*<sup>a</sup> from node A is higher or lower voltage according to Xc which is low or high resistance state (*R*on or *R*off). **Figure 7**, presents simulation results for a read operation in the crossbar structure. As it is discussed, to read the stored value of a cell we have to apply a spike like pulse to the C node of the cell and read the voltage from line ai, where bi line of the row and C node of the other cells in the same row are float. When *R*<sup>c</sup> is *R*off the voltage in node A is a low voltage that is equivalent to logic zero and vice versa, when *R*<sup>c</sup> has the value of *R*on, the voltage in node A has a higher voltage which represents to a logic one. **Figure 8**, presents two different cases. **Figure 8a**, shows reading '0' from a cell, when the neighbor stored '1' **Figure 8b**, shows reading '1' from a cell, when the neighbor stored '1'. In both cases target cell has been readout correctly. According to the simulation results

**Figure 8.**

*The simulations of memory cell in crossbar array for; (a) read of logic 0 from target cell and other cell, (b) read logic 1 from target cell and other. Figure reprinted by [9].*


#### **Table 3.**

*Comparison of read operation with previous works.*

*Development of Compute-in-Memory Memristive Crossbar Architecture with… DOI: http://dx.doi.org/10.5772/intechopen.99634*

and the formula presented in the [16], reading margin in this work is equal to the amount 0.7 V which can be a reasonable amount.

$$\text{RM} = \frac{\Delta Vout}{\Delta Vread} = \frac{\text{Vout}(LRS) - \text{Vout}(HRS)}{V\_{WS}} \tag{24}$$

where *V*WS is the read voltage applied. Simulation results are compared with previous works in **Table 3**. As it can be seen in this table, the proposed method is considerably better than [31, 32], and is similar to [15].
