*RF MEMS Switch Fabrication and Packaging DOI: http://dx.doi.org/10.5772/intechopen.95003*

ability to form a native oxide which has led to its wide usage in the IC industry. This

The main aim of using Silicon dioxide for RF MEMS switches is for the need for isolation and insulation from the low resistivity silicon wafer used as the substrate. By using Silicon Dioxide it is seen that the parasitics between the Co-Planar Waveguide (CPW) layer and the silicon substrate underneath are drastically reduced. This approach leads the application of silicon substrate for RF circuits and wireless communication systems [13–16]. The formation of oxide layer in this work is through the wet oxidation process since the requirement is only for passivation. The wafer was placed in a Nano pyrogenic furnace as shown in **Figure 2** to obtain a Silicon Dioxide layer of 1 μm thickness. The following steps were followed to oxidize the wafers. The time required for the Silicon Dioxide thickness of 1 μm

1.The furnace temperature is ramped to 500°C with Nitrogen gas flow at 5 liters/min. The furnace temperature is then raised to a temperature of

2.Once the set point temperature is reached, the wafers are put into a Quartz

3.During the heating up process, pure oxygen and hydrogen flows through the water bubbler for 4 hrs and 30 minutes resulting in gas saturation with water vapor.

4.The wafers were then annealed using Nitrogen gas with the gas allowed to flow

5.The wafers are then cooled for ten minutes and checked for oxide thickness.

The thickness of the oxide layer was measured using an ellipsometer and was

The proposed RF MEMS capacitive shunt switches have been integrated with a CPW line. The fabrication of CPW lines is easily integratable with the fabrication

layer serves a number of purposes. It acts as a surface passivation layer by protecting the surface from moisture and other atmospheric contaminants.

was calculated to be approximately 4 hours, 30 minutes.

*Nanofibers - Synthesis, Properties and Applications*

at 5 litre/min for 10 minutes.

found to be around 1.063 μm.

*1.1.3 CPW metal layer patterning*

*Details of oxidation furnace at CeNSe, IISc.*

**Figure 2.**

**256**

1100°C. This process of heating up takes 1–2 hours.

boat and loaded into the tube utilizing a furnace loader.

steps required for the RF MEMS switch, which justifies the choosing of CPW lines over microstrip lines. This section gives fabrication steps for the CPW layer formation on the Silicon wafer.


**Figure 3.** *TECPORT sputter coater.*

**Figure 4.** *EVG mask aligner at CeNSE, IISc.*

**Figure 5.** *Mask 1 for CPW layer patterning.*

etch and 10 to 20 sec for Cr etch. **Figures 5** and **6** represent the mask for patterning and the resulting CPW layer respectively.

gaseous materials into solid state, due to a chemical reaction occurring in the presence of plasma. PECVD uses electrical energy to generate the plasma. Due to the presence of plasma, the gas mixture is transformed into highly reactive ions and molecules, which leads to low temperature requirements as compared to CVD processes. PECVD processes results in high quality films which have good

Silane (SiH4) is usually supplied along with an inert gas like Nitrogen, Argon or Helium. Silane reacts with Ammonia (NH3) to produce Si3N4 and a byproduct Hydrogen. This reaction is as depicted by the chemical reaction as

3*SiH*<sup>4</sup> þ 4 *NH*<sup>3</sup> ! *Si*3*N*<sup>4</sup> þ 12 *H*<sup>2</sup>

depositing a positive photoresist AZ4562 by placing it on a spin coater. The spin coater rotates at 4000 rpm for 40 sec. After soft baking at 110°C for 1 minute, the PR is exposed to UV rays through a mask aligner at proximity of

b. **Lithography for Si3N4:** The patterning of Si3N4 is achieved by first

adhesion, uniformity and good step coverage [18].

given below.

*Oxford PECVD for Si3N4 deposition at CeNSE.*

**Figure 6.**

**Figure 7.**

**259**

*Optical microscope image.*

*RF MEMS Switch Fabrication and Packaging DOI: http://dx.doi.org/10.5772/intechopen.95003*
