*1.1.4 Dielectric layer deposition and patterning*

The following process steps were followed for the deposition and patterning of dielectric Silicon Nitride (Si3N4) on the central signal line of the CPW layer.

a. **Deposition of Si3N4:** This layer provides the dc isolation between the signal line and the ground line when the switch is actuated to the down-state position. A thinner layer of Si3N4 will result in a higher capacitance in the downstate but would lead to pinhole problems which occur in thin dielectric layers. Also, the thin dielectric layer must be able to withstand the actuation voltage without breakdown.

Oxford Instruments Plasma technology Plasma Enhanced Chemical Vapor Deposition (PECVD) system is used for deposition of Si3N4 as shown in **Figure 7**. PECVD is a process by which thin films are deposited from the conversion of

*RF MEMS Switch Fabrication and Packaging DOI: http://dx.doi.org/10.5772/intechopen.95003*

**Figure 6.** *Optical microscope image.*

**Figure 7.** *Oxford PECVD for Si3N4 deposition at CeNSE.*

gaseous materials into solid state, due to a chemical reaction occurring in the presence of plasma. PECVD uses electrical energy to generate the plasma. Due to the presence of plasma, the gas mixture is transformed into highly reactive ions and molecules, which leads to low temperature requirements as compared to CVD processes. PECVD processes results in high quality films which have good adhesion, uniformity and good step coverage [18].

Silane (SiH4) is usually supplied along with an inert gas like Nitrogen, Argon or Helium. Silane reacts with Ammonia (NH3) to produce Si3N4 and a byproduct Hydrogen. This reaction is as depicted by the chemical reaction as given below.

3*SiH*<sup>4</sup> þ 4 *NH*<sup>3</sup> ! *Si*3*N*<sup>4</sup> þ 12 *H*<sup>2</sup>

b. **Lithography for Si3N4:** The patterning of Si3N4 is achieved by first depositing a positive photoresist AZ4562 by placing it on a spin coater. The spin coater rotates at 4000 rpm for 40 sec. After soft baking at 110°C for 1 minute, the PR is exposed to UV rays through a mask aligner at proximity of

etch and 10 to 20 sec for Cr etch. **Figures 5** and **6** represent the mask for

The following process steps were followed for the deposition and patterning of

a. **Deposition of Si3N4:** This layer provides the dc isolation between the signal line and the ground line when the switch is actuated to the down-state position. A thinner layer of Si3N4 will result in a higher capacitance in the downstate but would lead to pinhole problems which occur in thin dielectric layers. Also, the thin dielectric layer must be able to withstand the actuation

Oxford Instruments Plasma technology Plasma Enhanced Chemical Vapor Deposition (PECVD) system is used for deposition of Si3N4 as shown in **Figure 7**. PECVD is a process by which thin films are deposited from the conversion of

dielectric Silicon Nitride (Si3N4) on the central signal line of the CPW layer.

patterning and the resulting CPW layer respectively.

*1.1.4 Dielectric layer deposition and patterning*

**Figure 4.**

**Figure 5.**

**258**

*Mask 1 for CPW layer patterning.*

*EVG mask aligner at CeNSE, IISc.*

*Nanofibers - Synthesis, Properties and Applications*

voltage without breakdown.

30 μm and energy of 110 mJ. The PR is then developed using the developer AZ 351B for 45–60 seconds. Next, the wafer is hard baked on an oven at 110°C for 3 minutes.

using Isopropyl Alchohol (IPA). This is to prevent the re-deposition of stripped photoresist on the substrate since Acetone has high vapor pressure. This is followed by cleaning with Ultrsonicate Acetone for 3 minutes.

The sacrificial layer is the layer which will be etched out to release the top metal layer. The topography and planarity of the top membrane is defined by the sacrificial layer planarity. Several materials like metals, dielectrics and photoresists have been used as the sacrificial layer. The choice of the sacrificial layer is based on the processing steps that follow the deposition of this layer, the temperature range, the required planarity and profile of surface. Here, a positive Photoresist (PR) S1813 is used as the sacrificial layer. This PR has to be deposited with utmost accuracy in order to define the gap between the top electrode and bottom electrode of the RF MEMS switch. The complete process of sacrificial layer deposition and patterning

**Sacrificial layer Optimization**: The PR S1813 is a positive photoresist which has excellent adhesion, excellent coating uniformity with effective broadband exposure. This PR is used for a wide variety of process flow requirements such as lift-off, dry etch, wet etch, the thickness of the PR to name a few. The plot in **Figure 11** gives the resist thickness versus spin for the Shipley family of PRs. Thick PR layers can be achieved in one step, however they have the disadvantage of being nonuniform over the wafer surface. In order to achieve uniform and thick PR coating, the coating process is performed in three steps. In the first step, the spin coater is run at low speeds of 500 rpm for 30 sec. This low spin speed and reduced spin time

**Figure 10** shows the patterned silicon nitride layer.

*1.1.5 Sacrificial layer deposition and patterning*

*RF MEMS Switch Fabrication and Packaging DOI: http://dx.doi.org/10.5772/intechopen.95003*

can be explained by the following steps:

*Optical microscope image of silicon nitride layer formed.*

**Figure 10.**

**Figure 11.**

**261**

*PR deposition using multiple step method.*

c. **Etching of Si3N4:** The etching of Si3N4 is performed using a dry etch process called Reactive Ion Etch (RIE). Reactive Ion etching is a process wherein the reactive species react with the material to be etched only when the surfaces of the material are activated by the collision of incident ions from the plasma. The etching characteristics like etch rate, etch profile, etch uniformity, etch selectivity can be controlled very precisely by selecting the right combination of recipes of chamber pressure, flow rate of gases, applied RF power and electrode bias. The etch rates are slow typically about 10 nm/ min up to 50 nm/min.

The RIE-F equipment used at CeNSe, IISc is as shown in **Figure 8**. For etching of Si3N4 the chamber pressure is set at 10 mTorr, RF power at 50 W with the main power at 2000 W. The flow rate of Sulfur Hexa Flouride (SF6) is set at 45 scc/m with the temperature at 5°C. For etching out 100 nm of Si3N4 the required time was 12 seconds. The mask used for the patterning of the Si3N4 layer is as shown in **Figure 9**.

d. **Photoresist strip:** This is followed by the wet etching of the photoresist by dipping the wafer in acetone for 5 minutes followed by immediate cleaning

**Figure 9.** *Mask 2 for silicon nitride.*

#### *RF MEMS Switch Fabrication and Packaging DOI: http://dx.doi.org/10.5772/intechopen.95003*

30 μm and energy of 110 mJ. The PR is then developed using the developer AZ 351B for 45–60 seconds. Next, the wafer is hard baked on an oven at 110°C

c. **Etching of Si3N4:** The etching of Si3N4 is performed using a dry etch process called Reactive Ion Etch (RIE). Reactive Ion etching is a process wherein the reactive species react with the material to be etched only when the surfaces of the material are activated by the collision of incident ions from the plasma. The

etching characteristics like etch rate, etch profile, etch uniformity, etch

selectivity can be controlled very precisely by selecting the right combination of recipes of chamber pressure, flow rate of gases, applied RF power and electrode bias. The etch rates are slow typically about 10 nm/ min up to 50 nm/min.

The RIE-F equipment used at CeNSe, IISc is as shown in **Figure 8**. For etching of Si3N4 the chamber pressure is set at 10 mTorr, RF power at 50 W with the main power at 2000 W. The flow rate of Sulfur Hexa Flouride (SF6) is set at 45 scc/m with the temperature at 5°C. For etching out 100 nm of Si3N4 the required time was 12 seconds. The mask used for the patterning of the Si3N4

d. **Photoresist strip:** This is followed by the wet etching of the photoresist by dipping the wafer in acetone for 5 minutes followed by immediate cleaning

for 3 minutes.

*Nanofibers - Synthesis, Properties and Applications*

layer is as shown in **Figure 9**.

**Figure 8.** *RIE F CeNSe, IISc.*

**Figure 9.**

**260**

*Mask 2 for silicon nitride.*

using Isopropyl Alchohol (IPA). This is to prevent the re-deposition of stripped photoresist on the substrate since Acetone has high vapor pressure. This is followed by cleaning with Ultrsonicate Acetone for 3 minutes. **Figure 10** shows the patterned silicon nitride layer.

## *1.1.5 Sacrificial layer deposition and patterning*

The sacrificial layer is the layer which will be etched out to release the top metal layer. The topography and planarity of the top membrane is defined by the sacrificial layer planarity. Several materials like metals, dielectrics and photoresists have been used as the sacrificial layer. The choice of the sacrificial layer is based on the processing steps that follow the deposition of this layer, the temperature range, the required planarity and profile of surface. Here, a positive Photoresist (PR) S1813 is used as the sacrificial layer. This PR has to be deposited with utmost accuracy in order to define the gap between the top electrode and bottom electrode of the RF MEMS switch. The complete process of sacrificial layer deposition and patterning can be explained by the following steps:

**Sacrificial layer Optimization**: The PR S1813 is a positive photoresist which has excellent adhesion, excellent coating uniformity with effective broadband exposure. This PR is used for a wide variety of process flow requirements such as lift-off, dry etch, wet etch, the thickness of the PR to name a few. The plot in **Figure 11** gives the resist thickness versus spin for the Shipley family of PRs. Thick PR layers can be achieved in one step, however they have the disadvantage of being nonuniform over the wafer surface. In order to achieve uniform and thick PR coating, the coating process is performed in three steps. In the first step, the spin coater is run at low speeds of 500 rpm for 30 sec. This low spin speed and reduced spin time

**Figure 10.** *Optical microscope image of silicon nitride layer formed.*

**Figure 11.** *PR deposition using multiple step method.*

will result in uniform coating of thick resist on the wafer. In the second step the speed is ramped upto 1000 rpm within a time of 30 sec. A solid film of the photoresist is formed with the complete evaporation of the solvent. This step decides the thickness and uniformity of the photoresist. The third step consists of the spin coater speed set at 2000 rpm for 40 sec. This last step ensures that any leftover solvent is completely evaporated. The complete cycle of spin coating is as shown in **Figure 11**. Using a Dektak optical profiler the thickness of this layer was confirmed to be 3 μm.

pressure of 6.5x10<sup>3</sup> Torr, target to substrate distance set at 7.5 cm, with the Argon flow rate at 250 sccm. The DC Power was set at 25 W with a pre sputtering time of 30 seconds followed by a deposition time of 1100 seconds

b. **Gold layer patterning:** The four switch designs chosen for the top Gold layer are shown as four respective masks in **Figure 13**. The lithography involved the use of AZ5412E positive PR. This was spin coated at 4000 rpm for 40 sec. The wafer was then soft baked aligner at a proximity of 10 μm and energy of 50 mJ The PR is then developed using the developer MF 26A with the wafer dipped in the developer of 20–140 sec. Next, the wafer is hard baked on an oven at 90°C for 30 minutes. For Gold etch, freshly made Potassium Iodide and Iodine (KI/I2) solution in a ratio of KI:I2:H2O = 4 g:1 g:40 ml is used. The unwanted Chrome deposition on the bottom layer is also etched out using a

A/sec.

The release of the top switch membrane is the most crucial step in the whole fabrication process. There are many methods to release the top layer without deformation and stiction. The first step in the top layer release is to etch the sacrificial layer. This could be achieved by using dry etching or wet etching. In wet etching, conventional liquid solvents are used to completely remove the sacrificial layer followed by drying. The drying could be through the process of air drying or

*Four top layer designs for RF MEMS switch. (a) Fixed-fixed beam switch. (b) Fixed-fixed Flexure switch.*

*(c) Fixed-Fixed Single Flexure switch. (d) Crab leg Flexure switch.*

with the deposition rate set at 50

*RF MEMS Switch Fabrication and Packaging DOI: http://dx.doi.org/10.5772/intechopen.95003*

Chrome etchant for 5 to 10 seconds.

*1.1.7 Top layer release*

through critical point drying.

**Figure 13.**

**263**

**Sacrificial layer patterning**: The patterning of the sacrificial layer photoresist is processes by first depositing one more layer of positive PR S1813 on this layer. This was achieved by the spin coater speed set to 500 rpm for 30 seconds, followed by a ramp up of 1000 rpm for 30 sec and 200 rpm for 40 sec. After soft baking the PR is exposed to UV rays through a mask aligner at a proximity of 30 μm and energy of 75 mJ. The mask used for generating the pattern for this layer is as shown in **Figure 12**.

The PR is then developed using the developer AZ 351B for 30–60 seconds. Next, the wafer is hard baked on an oven at 90°C for 30 minutes. The PR layer thickness shrunk from 3 μm to 2.09 μm after development and baking.

#### *1.1.6 Top layer deposition and patterning*

The top layer or beam formation defines the performance of the RF MEMS switch. The top layer designs were simulated using Coventorware™. These designs have been chosen due to their lower pull-in voltages. Gold is the choice for the top layer due to its favorable characteristics such as, its high conductivity, non-tarnishing property, high Young's Modulus and compatibility with micromachining processes. The top metal layer deposition and patterning is described in the following sections.

a. **Gold layer deposition:** The deposition of this layer was carried out using the TECPORT sputtering equipment. It may be recalled that the bottom layer has the composition of Cr/Au/Cr. This composition would lead to excellent adhesion of the top layer anchors with the previously deposited Chrome layer. Several Iterations were carried out in order to sputter the top Gold layer without residual stress. Several parameters such as temperature, rate of deposition were optimized in order to arrive at top layers without buckling after release process.

Finally, with the optimized parameters setting temperature and rate of deposition a stress free top layer was arrived at. The stress free top layer is of critical importance for reduction in actuation voltage. The process parameters of the sputter coater were set at a base pressure of 5x10<sup>6</sup> Torr, deposition

**Figure 12.** *Mask 3 for PR layer.*

pressure of 6.5x10<sup>3</sup> Torr, target to substrate distance set at 7.5 cm, with the Argon flow rate at 250 sccm. The DC Power was set at 25 W with a pre sputtering time of 30 seconds followed by a deposition time of 1100 seconds with the deposition rate set at 50 A/sec.

b. **Gold layer patterning:** The four switch designs chosen for the top Gold layer are shown as four respective masks in **Figure 13**. The lithography involved the use of AZ5412E positive PR. This was spin coated at 4000 rpm for 40 sec. The wafer was then soft baked aligner at a proximity of 10 μm and energy of 50 mJ The PR is then developed using the developer MF 26A with the wafer dipped in the developer of 20–140 sec. Next, the wafer is hard baked on an oven at 90°C for 30 minutes. For Gold etch, freshly made Potassium Iodide and Iodine (KI/I2) solution in a ratio of KI:I2:H2O = 4 g:1 g:40 ml is used. The unwanted Chrome deposition on the bottom layer is also etched out using a Chrome etchant for 5 to 10 seconds.
