**Figure 1.**

ability to form a native oxide which has led to its wide usage in the IC industry. This layer serves a number of purposes. It acts as a surface passivation layer by protecting the surface from moisture and other atmospheric contaminants.

steps required for the RF MEMS switch, which justifies the choosing of CPW lines over microstrip lines. This section gives fabrication steps for the CPW layer forma-

a. **Sputtering of Gold layer**: The sputtering of gold layer depends on various parameters such as temperature, target distance, deposition pressure and Argon flow rate [17]. TECPORT sputter coater is used for obtaining the Chrome/Gold layer as shown in **Figure 3**. The process parameters of the sputter coater were set at a base pressure of 5x10<sup>6</sup> Torr, deposition pressure of 6.5x10<sup>3</sup> Torr, target to substrate distance set at 7.5 cm, with the Argon flow rate at 250 Scc/m. A seed layer of 10 nm is sputtered using a DC power of 100 W, a pre-sputtering time of 600 seconds and a deposition time of 22 seconds. For Gold DC Power was set at 25 W with a pre sputtering time of 30 seconds followed by a deposition time of 220 seconds with the deposition

A/sec. This was followed by Chrome sputtering to form a layer of

15 nm thickness. This process step would ensure good adhesion of the anchors

pattern the CPW lines. A positive Photoresist (PR) AZ5214E is spin coated at speed of 4000 rpm using the spin coater for 40 seconds. It is then soft baked at 110°C for 1 minute. The wafer is then loaded into the EVG Mask aligner for PR exposure as shown in **Figure 4**. The proximity of the mask aligner is set at 30 μm and the energy for UV rays is set at 15 mJ. The mask used for this layer is as shown in **Figure 4**. The wafer is then post baked at 110°C for 1 minute and flood exposed using 75 mJ. The wafer is then immersed in the developer MF 26 A for around 20–30 seconds. The wafer is then subjected to a hard bake at 110°C for 3 minutes. The wafer is then inspected under the microscope to

c. **Gold/Chromium etch:** The etching of Gold (Au)/Chromium (Cr) is achieved by Potassium Iodide and Iodine (KI/I2) solution in a ratio of KI: I2: H2O = 4 g: 1 g: 40 ml. At room temperature etch rate is approximately 1 μm/min for Chrome/Gold. For the Cr/Au/Cr thicknesses of 10 nm/100 nm/15 nm respectively the time is set to 10 to 20 sec for Cr etch, 60 to 120 sec for Au

b. **Lithography for CPW layer**: The first photolithography step is used to

of the top Gold beam with the bottom layer.

ascertain that the PR has developed.

tion on the Silicon wafer.

*RF MEMS Switch Fabrication and Packaging DOI: http://dx.doi.org/10.5772/intechopen.95003*

rate at 5 <sup>0</sup>

**Figure 3.**

**257**

*TECPORT sputter coater.*

The main aim of using Silicon dioxide for RF MEMS switches is for the need for isolation and insulation from the low resistivity silicon wafer used as the substrate. By using Silicon Dioxide it is seen that the parasitics between the Co-Planar Waveguide (CPW) layer and the silicon substrate underneath are drastically reduced. This approach leads the application of silicon substrate for RF circuits and wireless communication systems [13–16]. The formation of oxide layer in this work is through the wet oxidation process since the requirement is only for passivation.

The wafer was placed in a Nano pyrogenic furnace as shown in **Figure 2** to obtain a Silicon Dioxide layer of 1 μm thickness. The following steps were followed to oxidize the wafers. The time required for the Silicon Dioxide thickness of 1 μm was calculated to be approximately 4 hours, 30 minutes.


The thickness of the oxide layer was measured using an ellipsometer and was found to be around 1.063 μm.

#### *1.1.3 CPW metal layer patterning*

The proposed RF MEMS capacitive shunt switches have been integrated with a CPW line. The fabrication of CPW lines is easily integratable with the fabrication

**Figure 2.** *Details of oxidation furnace at CeNSe, IISc.*
