**4. AC connected switching LED driver circuits**

LED driver circuits connected to the grid must meet several requirements regarding the frequency and the quality of the waveforms that are linked to the grid. The power factor must be controlled by means of a dedicated PFC circuit. Furthermore, it is necessary to keep the levels of Electromagnetic Interference (EMI) contents introduced into the grid low. Also, the flicker limits for LEDs must be considered.

In the design of drivers connected to the electrical network, before finding the circuit solutions it is essential to know the regulations and recommendations that an LED driver must comply with. The following design rules and standards must be taken into consideration.


To observe the design constraints, the driver circuit is composed of several modular blocks. Each block meets certain requirements. In **Figure 13**, the schematic of the LED driver for an AC lighting system is reported. From the line to the load (LED strings), there are the EMI filter, the diode rectifier, the PFC and the DC-DC converter. This schematization has been referred to as a dual-stage driver. If the power factor correction is integrated into the control in the DC-DC converter, then it is referred to as a single-stage driver.

#### **4.1 Flyback single stage LED driver circuit**

The single-stage LED driver is very attractive. On the other hand, it has to combine the control both the PF and the current to be supplied to the LEDs. The topology widely used in these applications is the Flyback converter especially at power rates below 100 W. The structure of the Flyback converter has the least

**Figure 13.** *Blocks schematic of a AC source LEDs driver circuit.*

*Passive and Active Topologies Investigation for LED Driver Circuits DOI: http://dx.doi.org/10.5772/intechopen.97098*

To reduce power losses with increasing efficiency, in higher power driver converter topologies, solutions with soft switching operation have been increasingly used. In these circuit types, the LLC resonant converter in half-bridge and fullbridge topologies are the most studied and applied [40]. The LLC resonant

In **Figure 12** qualitative estimation of the isolated power converter topologies

LED driver circuits connected to the grid must meet several requirements regarding the frequency and the quality of the waveforms that are linked to the grid. The power factor must be controlled by means of a dedicated PFC circuit. Furthermore, it is necessary to keep the levels of Electromagnetic Interference (EMI) contents introduced into the grid low. Also, the flicker limits for LEDs must

In the design of drivers connected to the electrical network, before finding the circuit solutions it is essential to know the regulations and recommendations that an LED driver must comply with. The following design rules and standards must be

• the ENERGY STAR® program recommendations, with specific regulations and

To observe the design constraints, the driver circuit is composed of several modular blocks. Each block meets certain requirements. In **Figure 13**, the schematic of the LED driver for an AC lighting system is reported. From the line to the load (LED strings), there are the EMI filter, the diode rectifier, the PFC and the DC-DC converter. This schematization has been referred to as a dual-stage driver. If the power factor correction is integrated into the control in the DC-DC converter, then

The single-stage LED driver is very attractive. On the other hand, it has to combine the control both the PF and the current to be supplied to the LEDs. The topology widely used in these applications is the Flyback converter especially at power rates below 100 W. The structure of the Flyback converter has the least

converter operation will be better discussed in the next section.

*Light-Emitting Diodes and Photodetectors - Advances and Future Directions*

**4. AC connected switching LED driver circuits**

requirements for LED lighting equipment [41],

• the harmonic standard (i.e. IEC 61000–3-2),

• flicker rules and metrics [14].

it is referred to as a single-stage driver.

*Blocks schematic of a AC source LEDs driver circuit.*

**4.1 Flyback single stage LED driver circuit**

versus the output power rate are shown.

be considered.

**Figure 13.**

**72**

taken into consideration.

components compared with other isolated converters, and many studies have been conducted on the grid connection to obtain high PF and low THD [42, 43]. In the LED driver application, the operative conditions usually used is a critical conduction mode (CRM) or the discontinuous conduction mode (DCM) [44]. In DCM (or CRM) the switch turn-on can be driven when the transformer is completely demagnetized, thus transformer saturation is avoided. The efficiency of the Flyback converter can be increased using the soft-switching technique exploiting the parasitic components present in the structure of the converter and of the power switch (**Figure 14a**). The quasi-resonant (QR) mode is used in the Flyback application to reduce the switching losses despite the non-constant frequency operation. Moreover, the QR operation allows has an enhanced transient response in DCM operation and it features a smaller EMI filter [45].

In addition, the QR Flyback LED driver has higher safety properties under output short circuit conditions. In the QR operation, the MOSFET is not turned on until the primary windings are fully demagnetized. On the other hand, a high ripple output current and high output diode and switch conduction losses in comparison to the fixed frequency driver. A further drawback well know is the high voltage stress on the switch given by

$$\mathbf{V}\_{\text{DS,peak}} = \mathbf{V}\_{\text{in}} + \frac{\mathbf{N}\_p}{\mathbf{N}\_s}\mathbf{V}\_0 + \mathbf{V}\_{\text{stray}} = \mathbf{V}\_{\text{in}} + \mathbf{V}\_r + \mathbf{V}\_{\text{stray}} \tag{12}$$

Where Vr is the output voltage reflected in the primary side and Vstray is the peak voltage of the ringing at turn-off transient due to the equivalent primary inductance Lps and the equivalent parasitic capacitance (Cps) composed by the output MOSFET capacitor and the equivalent primary side stray capacitor (**Figure 14a** and **b**). The resonant frequency *f*rs is

$$f\_{rs} = \frac{1}{2\pi\sqrt{L\_{ps} \bullet C\_{ps}}}\tag{13}$$

#### **Figure 14.**

*(a) Schematic of Flyback converter with the stray inductance and capacitance reported on the primary side. (b) DCM operation at td constant. (c) DCM in QR operation with k = 1.*

#### *Light-Emitting Diodes and Photodetectors - Advances and Future Directions*

In a DCM traditional operation flyback converter, the gate driver acts with a constant switching frequency, while in a QR operation a variable frequency is featured [46]. To turn on the switch a demagnetization time tM is necessary. After tM, a natural oscillation typical of a second-order system appears. The resonant frequency *f*<sup>r</sup> is lower than *f*rs and is related to the equivalent primary inductance Lp composed by the magnetization inductance LM and the equivalent stray inductance on the primary side Lps with the equivalent parasitic capacitance.

$$f\_r = \frac{1}{2\pi\sqrt{L\_p \bullet C\_{ps}}}\tag{14}$$

power average Pave and the apparent power in perfect sinusoidal waveforms the displacement power factor is equal to cosφ. Thus, in case of pure sinusoidal system,

In switching operative condition displacement power factor is established as

Where Vin1,rms and Iin1,rms are the first harmonic of the AC voltage and current

Neglecting the Harmonic beyond the first one is valid the approximation of Pavg1 related to the first harmonic quantities equal to Pavg, the true power factor can be established as the multiplication between the Distortion Power Factor and the

<sup>2</sup> <sup>p</sup> <sup>∙</sup> *Pavg*<sup>1</sup>

In switching converter, to obtain a high TPF two target can be pursued: low THDi and Displacement Power Factor very close to one. The control strategy target is to combine an input current quite close a sinusoidal waveform (high THD) with the same phase of the input voltage to reach high-PF. Furthermore, the common

Indeed, several integrated control chips for Flyback converter are based on the peak current PFC control implementing also QR operation [49]. A basic function block diagram of the QR peak current mode IC is depicted in **Figure 15a**. In **Figure 15a**, Vinr is the rectified AC line voltage. Vfb is the signal feedback of the output voltage V0. Vref is the reference voltage. The output of the error amplifier 1 is a multiplier factor of a

low to have in a slow variation of the output error (low pass filter effect) with a low ripple. The output of the multiplier block is proportional to Vinr. The signal voltage VRs is related to the primary inductor peak current. If VRs reaches the output voltage of the multiplier VMu the pulse width modulation (PWM) signal is reset turning off the power switch Q. The turn-on is achieved by the valley detect circuit (VDC) obtaining the waveforms depicted in **Figure 15b** The VDC acts after the full demagnetization of

*(a) PFC control circuit simplified schematic. (b) Primary and secondary side current behavior and driver*

*Vin*1,*rms* ∙*Iin*1,*rms*

*Vin i*ð Þ,*rms* ∙*Iin i*ð Þ,*rms* ∙ cos *φ* (19)

*Vin*1,*rms* ∙*Iin*1,*rms*

Vinr). The bandwidth of the error amplifier is quite

(18)

(20)

*PFdisp* <sup>¼</sup> *Pavg*

Displacement Power factor and True Power factor are equivalent.

*Passive and Active Topologies Investigation for LED Driver Circuits*

*Pavg* <sup>¼</sup> <sup>X</sup><sup>∞</sup>

*i*¼1

*TPF* <sup>¼</sup> <sup>1</sup> ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi

PFC control method is usually combined with a peak current control.

.

1 þ *THDi*

respectively. The Pavg is defined as

*DOI: http://dx.doi.org/10.5772/intechopen.97098*

Displacement Power Factor [48].

suitable reduced value of Vinr (kp

**Figure 15.**

*signal Vq.*

**75**

A simplified Flyback converter with the stray inductance and equivalent parasitic capacitor on the primary side linked to the AC source by a rectifier bridge is depicted in **Figure 14** a. In DCM operation at a constant frequency, a constant delay time td is added to tM to compose the turn-off time. In QR operation a resonant valley detection achieved by the control circuit is provided to switching at lower power losses. **Figure 14b** depicts the drain-source voltage waveforms and the current both in the primary and secondary side in DCM with constant frequency operation and QR operation with the turn-off at the first valley (**Figure 14c**).

The switching period Tsw is

$$T\_{sw} = t\_{on} + t\_M + t\_{oc} \tag{15}$$

Where tosc is the complete ringing time for the VDS

$$t\_{osc} = \frac{1}{2} [1 + 2(k - 1)] \frac{1}{f\_r} \tag{16}$$

As reduced load ton is reduced yet. At light load, the switching frequency is higher. Also, the ringing time tosc increase with the decrease of the load [47]. The quantitative k specifies the number of rings within tosc. Even, the number k is inversely proportional to the load. The control strategy acts considering the k to detect the better valley point to turn-off. At light load, the controller can be operated considering k different from 1 because the losses are still reduced. At high load, the k usually considered is equal to 1 to reduce drastically the losses.

#### **4.2 Control method to obtain high power factor**

The market requirements are based on standard IEC61000–3-2. It defines some input current THD targets (e.g., <10% at full power) that are very difficult to achieve, especially when working with lighting equipment over 25 W.

As know, the distortion corresponding to the harmonics contents. The distortion power factor DPF in the hypothesis of a perfectly sinusoidal input voltage is

$$DPF = \frac{1}{\sqrt{\mathbf{1} + T\mathbf{H}D\_i^{\cdot 2}}} = \frac{I\_{in1,rms}}{I\_{in,rms}} \tag{17}$$

Where THDi is the input current total harmonic distortion. The current Iin1,rms is the baseband component of the current, while Iin,rms is the total input current. The true Power Factor (TPF) in non-linear grid load such as the power converter is related to the Distortion Power Factor and the Displacement Power Factor.

The Displacement Power Factor is due to the phase shift between voltage and current at the fundamental line frequency. It is defined as the ratio between the real

In a DCM traditional operation flyback converter, the gate driver acts with a constant switching frequency, while in a QR operation a variable frequency is featured [46]. To turn on the switch a demagnetization time tM is necessary. After tM, a natural oscillation typical of a second-order system appears. The resonant frequency *f*<sup>r</sup> is lower than *f*rs and is related to the equivalent primary inductance Lp composed by the magnetization inductance LM and the equivalent stray inductance

*fr* <sup>¼</sup> <sup>1</sup>

2*π* ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi *Lp* ∙*Cps*

½ � 1 þ 2ð Þ *k* � 1

As reduced load ton is reduced yet. At light load, the switching frequency is higher. Also, the ringing time tosc increase with the decrease of the load [47]. The quantitative k specifies the number of rings within tosc. Even, the number k is inversely proportional to the load. The control strategy acts considering the k to detect the better valley point to turn-off. At light load, the controller can be operated considering k different from 1 because the losses are still reduced. At high load,

The market requirements are based on standard IEC61000–3-2. It defines some

As know, the distortion corresponding to the harmonics contents. The distortion

<sup>2</sup> <sup>p</sup> <sup>¼</sup> *Iin*1,*rms*

*Iin*,*rms*

1 þ *THDi*

Where THDi is the input current total harmonic distortion. The current Iin1,rms is the baseband component of the current, while Iin,rms is the total input current. The true Power Factor (TPF) in non-linear grid load such as the power converter is related to the Distortion Power Factor and the Displacement Power Factor.

The Displacement Power Factor is due to the phase shift between voltage and current at the fundamental line frequency. It is defined as the ratio between the real

input current THD targets (e.g., <10% at full power) that are very difficult to

power factor DPF in the hypothesis of a perfectly sinusoidal input voltage is

*DPF* <sup>¼</sup> <sup>1</sup> ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi

A simplified Flyback converter with the stray inductance and equivalent parasitic capacitor on the primary side linked to the AC source by a rectifier bridge is depicted in **Figure 14** a. In DCM operation at a constant frequency, a constant delay time td is added to tM to compose the turn-off time. In QR operation a resonant valley detection achieved by the control circuit is provided to switching at lower power losses. **Figure 14b** depicts the drain-source voltage waveforms and the current both in the primary and secondary side in DCM with constant frequency operation and QR operation with the turn-off at the first valley (**Figure 14c**).

<sup>p</sup> (14)

*Tsw* ¼ *ton* þ *tM* þ *tosc* (15)

(16)

(17)

1 *fr*

on the primary side Lps with the equivalent parasitic capacitance.

*Light-Emitting Diodes and Photodetectors - Advances and Future Directions*

Where tosc is the complete ringing time for the VDS

*tosc* <sup>¼</sup> <sup>1</sup> 2

the k usually considered is equal to 1 to reduce drastically the losses.

achieve, especially when working with lighting equipment over 25 W.

**4.2 Control method to obtain high power factor**

**74**

The switching period Tsw is

power average Pave and the apparent power in perfect sinusoidal waveforms the displacement power factor is equal to cosφ. Thus, in case of pure sinusoidal system, Displacement Power factor and True Power factor are equivalent.

In switching operative condition displacement power factor is established as

$$PF\_{disp} = \frac{P\_{avg}}{V\_{in1,rms} \bullet I\_{in1,rms}} \tag{18}$$

Where Vin1,rms and Iin1,rms are the first harmonic of the AC voltage and current respectively. The Pavg is defined as

$$P\_{\text{avg}} = \sum\_{i=1}^{\infty} V\_{in(i),rms} \bullet I\_{in(i),rms} \bullet \cos \phi \tag{19}$$

Neglecting the Harmonic beyond the first one is valid the approximation of Pavg1 related to the first harmonic quantities equal to Pavg, the true power factor can be established as the multiplication between the Distortion Power Factor and the Displacement Power Factor [48].

$$TPF = \frac{1}{\sqrt{\mathbf{1} + THD\_i^2}} \bullet \frac{P\_{avg1}}{V\_{in1,rms} \bullet I\_{in1,rms}} \tag{20}$$

In switching converter, to obtain a high TPF two target can be pursued: low THDi and Displacement Power Factor very close to one. The control strategy target is to combine an input current quite close a sinusoidal waveform (high THD) with the same phase of the input voltage to reach high-PF. Furthermore, the common PFC control method is usually combined with a peak current control.

Indeed, several integrated control chips for Flyback converter are based on the peak current PFC control implementing also QR operation [49]. A basic function block diagram of the QR peak current mode IC is depicted in **Figure 15a**. In **Figure 15a**, Vinr is the rectified AC line voltage. Vfb is the signal feedback of the output voltage V0. Vref is the reference voltage. The output of the error amplifier 1 is a multiplier factor of a suitable reduced value of Vinr (kp . Vinr). The bandwidth of the error amplifier is quite low to have in a slow variation of the output error (low pass filter effect) with a low ripple. The output of the multiplier block is proportional to Vinr. The signal voltage VRs is related to the primary inductor peak current. If VRs reaches the output voltage of the multiplier VMu the pulse width modulation (PWM) signal is reset turning off the power switch Q. The turn-on is achieved by the valley detect circuit (VDC) obtaining the waveforms depicted in **Figure 15b** The VDC acts after the full demagnetization of

**Figure 15.** *(a) PFC control circuit simplified schematic. (b) Primary and secondary side current behavior and driver signal Vq.*

the primary windings provided by an enable signal of a demagnetization detection circuit (DDC). The output signal of the VDC block set the delay time td. As shown in **Figure 15b** the current envelope both at the primary and secondary side is a half sinusoidal cycle. In particular, the inductor peak current will be a sine wave with the same phase as the input voltage, which can achieve a quite high-power factor. As above described, the control signal Vq has a non-constant frequency.

The controller can be used in the simple DCM operation without QR enhancement, replacing the VDC block with only the DDC and settling the delay time td at a constant value. In this last control approach, the driver signal Vq acts at constant frequency.

The control method investigation is based on the analysis detailed in [47, 50]. The control method quantities depending on the instantaneous line voltage. For simplicity of analysis in the following, the term θ = 2π*f*linet is considered. Where *f*line is the frequency of the grid line quantities. Furthermore, the analysis is based on the following hypothesis.


Based on the first assumption the voltage downstream the rectifier bridge is a rectified sinusoidal waveform.

$$V\_{inr}(\theta) = V\_{inr\_dpk} \bullet \sin \theta \tag{21}$$

Considering the assumption of k = 1 and neglecting the td for simplicity (very

From (24) the minimum value of the stitching frequency *f*sw,min is achieved at

∙ 1 þ

<sup>∙</sup> <sup>1</sup> <sup>1</sup> <sup>þ</sup> *Vinr*,*peak Vr*

*Vr* sin *θ*

*Vinr*,*pk* <sup>∙</sup> sin *<sup>θ</sup>* <sup>∙</sup> *<sup>t</sup>*

2 *on*ð Þ*θ*

∙ *Vinr*,*pk* ∙ sin *θ* ∙*ton* (29)

2 *on*ð Þ*θ*

*Tsw*ð Þ*<sup>θ</sup>* (30)

*Tsw*ð Þ*<sup>θ</sup>* <sup>¼</sup> *constant* (31)

<sup>¼</sup> <sup>1</sup> <sup>1</sup> <sup>þ</sup> *Vinr*,*peak*

The control strategy described above in **Figure 15b** leads to the envelope current on

The rectified input current Iinr(θ) can be established as the average value of the

2*LM*

The two-stage driver converter is more expensive in terms of components used but offering better immunity to line disturbances and greater flexibility because the power factor control is separated by the DC-DC current allowing more simple dimmable applications. Furthermore, the modular The wide solution for the PFC topology is a boost converter. In power converters such as the Boost (also the SEPIC and ĆuK converter, but with more numerous components than the Boost) the switch non directly disconnect the power source (see **Figure 7**). This causes a not complete interruption of the input current such as in the Buck or Buck-Boost topologies. Furthermore, the current ripple can be smoothly controlled from the converter, making the Boost topology very attractive for active PFC. To increase the

<sup>∙</sup> *Tsw*ð Þ¼ *<sup>θ</sup> <sup>t</sup>*

The constraint design condition for achieve a displacement power factor

the primary stage following the sinusoid described by (22) and better specified as

*Vinr*,*pk Vr*

∙j j sin *θ* (26)

(27)

(28)

*Vinr*,*pk*

*fsw* <sup>¼</sup> *Vinr*,*pk LM* ∙*Ip*,*PK*

*<sup>d</sup>*ð Þ¼ *<sup>θ</sup> ton TSW*

*Ip*,*pk* <sup>¼</sup> <sup>1</sup> *LM*

<sup>2</sup> <sup>∙</sup>*Ip*,*pk*ð Þ*<sup>θ</sup>* <sup>∙</sup> *ton*ð Þ*<sup>θ</sup>*

ð Þ*<sup>θ</sup>* <sup>∙</sup> *TSW*ð Þ¼ *<sup>θ</sup> ton*ð Þ*<sup>θ</sup>*

primary current in each triangle over a switching cycle (**Figure 15b**).

*Tsw*ð Þ*<sup>θ</sup>* <sup>¼</sup> <sup>1</sup>

*Tsw*ð Þ*θ* <sup>2</sup>

power rate requested an interleaved solution can be adopted [51].

The second stage DC-DC converter topology depends on the power rate requested. Over the 100 W Half and Full Bridge topologies are implemented as described in **Figure 12**. Usually, an isolated resonant converter is considered to increase the efficiency and reduce the EMI contents. In the resonant topologies, the

close to the CRM operation). The switching time Tsw is given by

*Tsw* <sup>¼</sup> *ton* <sup>þ</sup> *toff* <sup>¼</sup> *LM* <sup>∙</sup>*Ip*,*PK*

*Passive and Active Topologies Investigation for LED Driver Circuits*

sin*θ* = 1 (the peak of the rectified sinusoid).

*DOI: http://dx.doi.org/10.5772/intechopen.97098*

The duty cycle is given by

*Iinr*ð Þ¼ *<sup>θ</sup>* <sup>1</sup>

*d*2

**4.3 Two-stage LED driver circuits**

equal to 1 is

**77**

Where Vinr,peak is the max peak amplitude of the rectified Vinr.

The current peak Ip,pk at the primary side is enveloped by a rectified sinusoid as shown in **Figure 15b**. It is given by. It is given by

$$I\_{p,pk}(\theta) = I\_{p,PK} \bullet \sin \theta \tag{22}$$

Where Ip,PK is the maximum peak amplitude of the enveloped current in the primary side. In the secondary side the Is,pk is proportional to the primary current.

$$I\_{s,pk}(\theta) = n \bullet I\_{p,pk} \tag{23}$$

Where n is the transform ratio, n = Np/Ns.

Considering the current Ip as a triangle form, as shown in **Figure 14b** and **c**, ton is expressed by

$$t\_{\rm on} = \frac{L\_M \bullet I\_{p,pk}(\theta)}{V\_{\rm inr}(\theta)}\tag{24}$$

At turn-off, toff is

$$t\_{\it eff} = \frac{L\_s \bullet I\_{s,pk}(\theta)}{V\_0} = \frac{L\_M \bullet I\_{p,pk(\theta)}}{n \bullet V\_0} \tag{25}$$

*Passive and Active Topologies Investigation for LED Driver Circuits DOI: http://dx.doi.org/10.5772/intechopen.97098*

Considering the assumption of k = 1 and neglecting the td for simplicity (very close to the CRM operation). The switching time Tsw is given by

$$T\_{sw} = t\_{on} + t\_{off} = \frac{L\_M \bullet I\_{p, PK}}{V\_{inr,pk}} \bullet \left[ \mathbf{1} + \frac{V\_{inr,pk}}{V\_r} \bullet |\sin\theta| \right] \tag{26}$$

From (24) the minimum value of the stitching frequency *f*sw,min is achieved at sin*θ* = 1 (the peak of the rectified sinusoid).

$$f\_{sw} = \frac{V\_{inr,pk}}{L\_M \bullet I\_{p,PK}} \bullet \frac{1}{1 + \frac{V\_{inr,peak}}{V\_r}} \tag{27}$$

The duty cycle is given by

the primary windings provided by an enable signal of a demagnetization detection circuit (DDC). The output signal of the VDC block set the delay time td. As shown in **Figure 15b** the current envelope both at the primary and secondary side is a half sinusoidal cycle. In particular, the inductor peak current will be a sine wave with the same phase as the input voltage, which can achieve a quite high-power factor. As

The controller can be used in the simple DCM operation without QR enhancement, replacing the VDC block with only the DDC and settling the delay time td at a constant value. In this last control approach, the driver signal Vq acts at constant frequency. The control method investigation is based on the analysis detailed in [47, 50]. The control method quantities depending on the instantaneous line voltage. For simplicity of analysis in the following, the term θ = 2π*f*linet is considered. Where *f*line is the frequency of the grid line quantities. Furthermore, the analysis is based on the

above described, the control signal Vq has a non-constant frequency.

*Light-Emitting Diodes and Photodetectors - Advances and Future Directions*

• The coupling between the inductors on the Flyback is ideal.

• The Flyback converter operates in DCM and QR with k = 1

Where Vinr,peak is the max peak amplitude of the rectified Vinr.

• The output voltage is constant in a line half-cycle.

shown in **Figure 15b**. It is given by. It is given by

Where n is the transform ratio, n = Np/Ns.

• The power switch and the diodes have conduction and switching losses

Based on the first assumption the voltage downstream the rectifier bridge is a

The current peak Ip,pk at the primary side is enveloped by a rectified sinusoid as

Where Ip,PK is the maximum peak amplitude of the enveloped current in the primary side. In the secondary side the Is,pk is proportional to the primary current.

Considering the current Ip as a triangle form, as shown in **Figure 14b** and **c**, ton is

*ton* <sup>¼</sup> *LM* <sup>∙</sup>*Ip*,*pk*ð Þ*<sup>θ</sup>*

<sup>¼</sup> *LM* <sup>∙</sup>*Ip*,*pk*ð Þ*<sup>θ</sup> n* ∙*V*<sup>0</sup>

*toff* <sup>¼</sup> *Ls* <sup>∙</sup>*Is*,*pk*ð Þ*<sup>θ</sup> V*<sup>0</sup>

*Vinr*ð Þ¼ *θ Vinr*,*pk* ∙ sin *θ* (21)

*Ip*,*pk*ð Þ¼ *θ Ip*,*PK* ∙*sinθ* (22)

*Is*,*pk*ð Þ¼ *θ n* ∙*Ip*,*pk* (23)

*Vinr*ð Þ*<sup>θ</sup>* (24)

(25)

following hypothesis.

negligible).

expressed by

**76**

At turn-off, toff is

rectified sinusoidal waveform.

• The input voltage Vin is fully sinusoidal.

$$d(\theta) = \frac{t\_{on}}{T\_{SW}} = \frac{1}{1 + \frac{V\_{iw,peak}}{V\_r} \sin \theta} \tag{28}$$

The control strategy described above in **Figure 15b** leads to the envelope current on the primary stage following the sinusoid described by (22) and better specified as

$$I\_{p,pk} = \frac{1}{L\_M} \bullet \left(V\_{inr,pk} \bullet \sin \theta\right) \bullet t\_{on} \tag{29}$$

The rectified input current Iinr(θ) can be established as the average value of the primary current in each triangle over a switching cycle (**Figure 15b**).

$$I\_{inr}(\theta) = \frac{1}{2} \bullet I\_{p,pk}(\theta) \bullet \frac{t\_{on}(\theta)}{T\_{sw}(\theta)} = \frac{1}{2L\_M} (V\_{inr,pk} \bullet \sin \theta) \bullet \frac{t\_{on}^2(\theta)}{T\_{sw}(\theta)}\tag{30}$$

The constraint design condition for achieve a displacement power factor equal to 1 is

$$d^2(\theta) \bullet T\_{SW}(\theta) = \left[\frac{t\_{on}(\theta)}{T\_{sw}(\theta)}\right]^2 \bullet T\_{sw}(\theta) = \frac{t\_{on}^2(\theta)}{T\_{sw}(\theta)} = constant \tag{31}$$

#### **4.3 Two-stage LED driver circuits**

The two-stage driver converter is more expensive in terms of components used but offering better immunity to line disturbances and greater flexibility because the power factor control is separated by the DC-DC current allowing more simple dimmable applications. Furthermore, the modular The wide solution for the PFC topology is a boost converter. In power converters such as the Boost (also the SEPIC and ĆuK converter, but with more numerous components than the Boost) the switch non directly disconnect the power source (see **Figure 7**). This causes a not complete interruption of the input current such as in the Buck or Buck-Boost topologies. Furthermore, the current ripple can be smoothly controlled from the converter, making the Boost topology very attractive for active PFC. To increase the power rate requested an interleaved solution can be adopted [51].

The second stage DC-DC converter topology depends on the power rate requested. Over the 100 W Half and Full Bridge topologies are implemented as described in **Figure 12**. Usually, an isolated resonant converter is considered to increase the efficiency and reduce the EMI contents. In the resonant topologies, the

The control loop to obtain the average current mode maintains the current proportional to the input voltage. While the voltage control loop regulates the

• the high quality of input current waveforms with reduced inductor current

• the need to insert a compensation network in the current amplifier which takes into account the characteristics of the converter used and the duty point during

In **Figure 17b** the inductor average current behavior and the inductor current ripple are shown. The value of ΔILs is chosen during the design phase in the range from 20 to 25% of the peak of the input current Iin. The input peak current in the

> ffiffi 2 <sup>p</sup> <sup>∙</sup> *Pin*, *max Vin*,*rms*, *min*

Where Pin,max is the input power at the maximum output power requested. It is

*Pin*, *max* <sup>¼</sup> *<sup>P</sup>*0, *max*

*ILs*,*pk* ¼ *Iin*,*pk* þ

Where KΔ<sup>I</sup> is the inductor ripple factor (supposing 20% of the ΔIL maximum, KΔ<sup>I</sup> = 0.20). To design the Boost inductance, the duty cycle at the peak of the minimum sinusoidal input voltage is considered. The value of the rectified voltage is

2

*Vin*,*pk*, *min* <sup>¼</sup> ffiffi

*ηmin*

Δ*ILs*

<sup>2</sup> (34)

Δ*ILs* ¼ *K*Δ*<sup>I</sup>* ∙*Iin*,*pk* (35)

<sup>p</sup> <sup>∙</sup>*Vin*,*pk*, *min* ð Þ*<sup>θ</sup>* (36)

(32)

(33)

*Iin*,*pk* ¼

The advantages of the average current control are the following

• the maximum peak current in the switching device is reduced

output voltage to the boost value requested.

*DOI: http://dx.doi.org/10.5772/intechopen.97098*

*Passive and Active Topologies Investigation for LED Driver Circuits*

• little sensitivity to switching noises;

• the need to sense the current in the inductor;

case of pure sinusoidal waveform is given by

With ηmin is the minimum converter efficiency.

The peak inductor current is

• a constant switching frequency:

The disadvantages concern

the line voltage cycle.

ripple

given by

Where

obtained from

**79**

**Figure 16.**

*Two stage LED driver circuit composed by PFC boost converter and half-bridge LLC converter.*

LLC converter is mainly adopted in LED driver applications because of its softswitching characteristic. The LLC converter features zero-voltage switching turnon of the switches on the primary side and zero-current turn-off for the rectifier diodes on the secondary side. The soft-switching transients allow both low noises and reduced stress during the switches transients. In addition, the LLC converter regulates the output voltage in a wide-output voltage. Moreover, the isolated highfrequency transformer allows a multi-output driver circuit for the string LEDs solution. In **Figure 16** two stage LED driver composed by a Boost PFC converter and Half-Bridge LLC converter useful for load until 500 W is reported.

#### **4.4 Boost PFC circuit evaluation**

The Boost PFC converter has a simple topology. The switch driver circuit is referenced to the ground reducing the driver switching noises. Furthermore, it can guarantee a power factor close to one obtainable with several control techniques [52]. It allows an input current with low distortion and an output voltage with a very low ripple thanks to the presence of the capacitor Cs. On the other hand, the presence of the capacitor Cs produces high currents during converter switching on and has an intrinsic weakness in the short circuit as the output is connected directly to the input by means of the inductor Ls. At higher powers, it needs to run on CCM to ensure adequate power transfer. In this operation mode, the current in the inductor never reaches zero during the switching cycle. Usually, the most used controllers for these applications are based on the average current control that allows CCM operation. The Boost PFC scheme with the average current control is described in **Figure 17**.

**Figure 17.** *(a) Simplified block scheme of the boost PFC with average current control. (b) Inductor average and ripple currents.*

The control loop to obtain the average current mode maintains the current proportional to the input voltage. While the voltage control loop regulates the output voltage to the boost value requested.

The advantages of the average current control are the following


The disadvantages concern

LLC converter is mainly adopted in LED driver applications because of its softswitching characteristic. The LLC converter features zero-voltage switching turnon of the switches on the primary side and zero-current turn-off for the rectifier diodes on the secondary side. The soft-switching transients allow both low noises and reduced stress during the switches transients. In addition, the LLC converter regulates the output voltage in a wide-output voltage. Moreover, the isolated highfrequency transformer allows a multi-output driver circuit for the string LEDs solution. In **Figure 16** two stage LED driver composed by a Boost PFC converter

*Two stage LED driver circuit composed by PFC boost converter and half-bridge LLC converter.*

*Light-Emitting Diodes and Photodetectors - Advances and Future Directions*

and Half-Bridge LLC converter useful for load until 500 W is reported.

The Boost PFC converter has a simple topology. The switch driver circuit is referenced to the ground reducing the driver switching noises. Furthermore, it can guarantee a power factor close to one obtainable with several control techniques [52]. It allows an input current with low distortion and an output voltage with a very low ripple thanks to the presence of the capacitor Cs. On the other hand, the presence of the capacitor Cs produces high currents during converter switching on and has an intrinsic weakness in the short circuit as the output is connected directly to the input by means of the inductor Ls. At higher powers, it needs to run on CCM to ensure adequate power transfer. In this operation mode, the current in the inductor never reaches zero during the switching cycle. Usually, the most used controllers for these applications are based on the average current control that allows CCM operation. The

Boost PFC scheme with the average current control is described in **Figure 17**.

*(a) Simplified block scheme of the boost PFC with average current control. (b) Inductor average and ripple*

**4.4 Boost PFC circuit evaluation**

**Figure 16.**

**Figure 17.**

*currents.*

**78**


In **Figure 17b** the inductor average current behavior and the inductor current ripple are shown. The value of ΔILs is chosen during the design phase in the range from 20 to 25% of the peak of the input current Iin. The input peak current in the case of pure sinusoidal waveform is given by

$$I\_{in,pk} = \frac{\sqrt{2} \bullet P\_{in,max}}{V\_{in,rms,min}} \tag{32}$$

Where Pin,max is the input power at the maximum output power requested. It is given by

$$P\_{\rm in,max} = \frac{P\_{\rm O,max}}{\eta\_{\rm min}} \tag{33}$$

With ηmin is the minimum converter efficiency. The peak inductor current is

$$I\_{Ls\_{\rm pkl}} = I\_{in\_{\rm pkl}} + \frac{\Delta I\_{Ls}}{2} \tag{34}$$

Where

$$
\Delta I\_{Ls} = K\_{\Delta I} \bullet I\_{in,pk} \tag{35}
$$

Where KΔ<sup>I</sup> is the inductor ripple factor (supposing 20% of the ΔIL maximum, KΔ<sup>I</sup> = 0.20). To design the Boost inductance, the duty cycle at the peak of the minimum sinusoidal input voltage is considered. The value of the rectified voltage is obtained from

$$V\_{in,pk,min} = \sqrt{2} \bullet V\_{in,pk,min} \left(\theta\right) \tag{36}$$

The duty cycle at the minimum input voltage and considering the required output voltage (approximately it is a constant voltage) is calculated by

$$d = \frac{V\_0 - V\_{in,pk,min}}{V\_0} \tag{37}$$

• Use of the power semiconductor devices with a less current rate.

*Passive and Active Topologies Investigation for LED Driver Circuits*

*DOI: http://dx.doi.org/10.5772/intechopen.97098*

structure.

is shown in **Figure 18**.

**Figure 18.**

**81**

*Three channel boost PFC simplified electrical scheme.*

**4.5 Half-bridge LLC converter notes**

• Reduction of conduction diode and MOSFET losses thanks to the parallel

In the interleaved topology the reduced current ripple allows to avoid the capacitor Cin. A complete design of 3 kW PFC based on an interleaved PFC Boost converter is reported in [54]. The control technique is based on Microcontroller Units (MCUs) or specialized Integrated Circuits (ICs). An example of the highperformance IC controller of common use is the FAN9673 (On-Semiconductor) [55]. It is an interleaved threechannel CCM PFC controller, implementing a channel management function. It enables a single cell at light load (less than one-third of the rated load) or two or three cells depending on power level request. The interleaved cells management optimizes PFC efficiency. Three legs interleaved Boost PFC schematic linked to the line grid by a diode rectifier bridge and EMI filter

LLC resonant converter in its half-bridge implementation is more popular in LED driver circuit for the low switching noise and the capability to achieve a highpower density. An HF transformer is used to attain galvanic isolation. A compact volume is obtained by integrating part of the resonant tank into the HF transformer sizing. In this design approach, the transformer arrangement leads to satisfying the requirements on LM and LR, thus avoiding adding additional external components. Thus, the transformer inductive parameters and a series-connected capacitor CR are used to make a resonant tank. The LLC solution allows Buck and Boost transfer characteristics in the soft-switching operative region. The switching devices Q1 and Q2 operate at a duty cycle of just under 50% to avoid cross conduction. The output voltage is regulated through a variation of the converter switching frequency. The converter features two resonant frequencies. The resonant frequency depends of the resonant tank components and the load conditions. The higher resonant

then, the inductance Ls is given by

$$L\_s = \frac{V\_{in,plt,min} \bullet d}{f\_{sw} \bullet \Delta I\_{L\_r}} \tag{38}$$

The purpose of the output capacitor Cin in **Figure 17a** is to filter the high-frequency current component of the inductance.

The HF capacitor acts as an EMI filter minimizing the HF harmonic component (this HF current component are shorted by Cin) [53].

The HF capacitor design is a trade-off to minimize the noise injected into the line grid and the value that avoid zero-crossing line current distortion. Cin is given by

$$C\_{in} = K\_{\Delta I} \bullet \frac{I\_{in,pk}}{2\pi \bullet f\_{sv} \bullet r \bullet V\_{in,pk,min}} \tag{39}$$

Where KΔ<sup>I</sup> = 0.20 and *r* is input voltage ripple factor (ΔVin/Vin) settled usually in the range of 5–6%. An HF film capacitor with low ESL and high-voltage rating (630 V for European line voltage of 230 V). Usually, ceramic technology capacitor is selected for this converter application.

The output capacitor selection C0 is related to the output voltage maximum ripple required (ΔV0). C0 is calculated by

$$C\_0 \ge \frac{P\_0}{2\pi \cdot f\_{sw} \Delta V\_0 \bullet V\_0} \tag{40}$$

As the required power increases (≥500 W), the PFC converter performances can be optimized by adopting an interleaved solution. The interleaved Boost topology is obtained connecting two or more single Boost legs as shown in **Figure 18**, controlling the switching of every MOSFET with a proper control strategy.

The command signals of the switches are supplied in out of phase mode according to

$$h \, phase \, h \dot{y}t = \frac{360^{\circ}}{N\_c} \tag{41}$$

where Nc is the number of legs in the interleaved boost circuit. Despite the increase in the number of components and a more complex control technique, in the interleaved topologies several advantages are shown.


In the interleaved topology the reduced current ripple allows to avoid the capacitor Cin. A complete design of 3 kW PFC based on an interleaved PFC Boost converter is reported in [54]. The control technique is based on Microcontroller Units (MCUs) or specialized Integrated Circuits (ICs). An example of the highperformance IC controller of common use is the FAN9673 (On-Semiconductor) [55]. It is an interleaved threechannel CCM PFC controller, implementing a channel management function. It enables a single cell at light load (less than one-third of the rated load) or two or three cells depending on power level request. The interleaved cells management optimizes PFC efficiency. Three legs interleaved Boost PFC schematic linked to the line grid by a diode rectifier bridge and EMI filter is shown in **Figure 18**.

#### **4.5 Half-bridge LLC converter notes**

The duty cycle at the minimum input voltage and considering the required

*<sup>d</sup>* <sup>¼</sup> *<sup>V</sup>*<sup>0</sup> � *Vin*,*pk*, *min V*<sup>0</sup>

*Ls* <sup>¼</sup> *Vin*,*pk*, *min* <sup>∙</sup> *<sup>d</sup> fsw* ∙Δ*ILs*

The HF capacitor acts as an EMI filter minimizing the HF harmonic component

Where KΔ<sup>I</sup> = 0.20 and *r* is input voltage ripple factor (ΔVin/Vin) settled usually in the range of 5–6%. An HF film capacitor with low ESL and high-voltage rating (630 V for European line voltage of 230 V). Usually, ceramic technology capacitor is

The output capacitor selection C0 is related to the output voltage maximum

As the required power increases (≥500 W), the PFC converter performances can be optimized by adopting an interleaved solution. The interleaved Boost topology is obtained connecting two or more single Boost legs as shown in **Figure 18**, controlling the switching of every MOSFET with a proper control strategy. The command signals of the switches are supplied in out of phase mode

*phaseshift* <sup>¼</sup> 360°

where Nc is the number of legs in the interleaved boost circuit. Despite the increase in the number of components and a more complex control technique, in

• Reduced electromagnetic contents and consequently EMI filter.

*Nc*

*P*0 2*π* ∙ *fsw*Δ*V*<sup>0</sup> ∙*V*<sup>0</sup>

*C*<sup>0</sup> ≥

the interleaved topologies several advantages are shown.

• Reduction of the magnetics components size.

• RMS current rating decrease in the output capacitance.

• Reduced overall input current ripple.

2*π* ∙ *fsw* ∙*r*∙*Vin*,*pk*, *min*

The HF capacitor design is a trade-off to minimize the noise injected into the line grid and the value that avoid zero-crossing line current distortion. Cin is

*Cin* <sup>¼</sup> *<sup>K</sup>*Δ*<sup>I</sup>* <sup>∙</sup> *Iin*,*pk*

The purpose of the output capacitor Cin in **Figure 17a** is to filter the

(37)

(38)

(39)

(40)

(41)

output voltage (approximately it is a constant voltage) is calculated by

*Light-Emitting Diodes and Photodetectors - Advances and Future Directions*

then, the inductance Ls is given by

selected for this converter application.

ripple required (ΔV0). C0 is calculated by

given by

according to

**80**

high-frequency current component of the inductance.

(this HF current component are shorted by Cin) [53].

LLC resonant converter in its half-bridge implementation is more popular in LED driver circuit for the low switching noise and the capability to achieve a highpower density. An HF transformer is used to attain galvanic isolation. A compact volume is obtained by integrating part of the resonant tank into the HF transformer sizing. In this design approach, the transformer arrangement leads to satisfying the requirements on LM and LR, thus avoiding adding additional external components. Thus, the transformer inductive parameters and a series-connected capacitor CR are used to make a resonant tank. The LLC solution allows Buck and Boost transfer characteristics in the soft-switching operative region. The switching devices Q1 and Q2 operate at a duty cycle of just under 50% to avoid cross conduction. The output voltage is regulated through a variation of the converter switching frequency. The converter features two resonant frequencies. The resonant frequency depends of the resonant tank components and the load conditions. The higher resonant

**Figure 18.** *Three channel boost PFC simplified electrical scheme.*

frequency *f*R1 occurs considering the higher load conditions. In this case the LM can be neglected and *f*R1 is given by

$$f\_{r1} = \frac{1}{2\pi \bullet \sqrt{\mathbf{L}\_R \bullet \mathbf{C}\_R}} \tag{42}$$

operative condition, on the primary-side switches, the ZVS is reached. Finally, the

In the switching frequency between the two resonant frequencies (*f*r2 > *f*sw > *f*r1). The resonant tank gives a voltage gain higher than unity. The primary-side switches commutate in ZVS and in the secondary-side diodes achieve ZCS. In this operative condition, the peak value of the resonant current circulating through the LM is larger leading to higher conduction losses through the converter. Based on the load the equivalent impedance connected to the half-bridge switching leg can be either inductive or capacitive at frequency variation. Usually, the LLC converter operates in the region where the input impedance of the resonant tank has an inductive behavior (i.e. it increases with *f*sw) [59]. Furthermore, the ZVS mode on the primary-side is achieved only if the tank input impedance Zir is inductive. This operative condition can be controlled by changing the switching frequency. Higher

In the LED driver application, the output current must be controlled. In LLC the current mode controller is arranged with a voltage-controlled oscillator (VCO) that change the current control signal in variable switching frequency to drive the primary-side MOSFETs [60]. A simplified schematic of the current control with the VCO block is depicted in **Figure 19c**. The drawback of the LLC converter results from the difficulty in achieving consistent dynamic performance over wide-operating conditions. To reduce the switching losses on the secondary-side a synchronous rectifier solution may be arranged. In this case the diodes are replaced by low voltage

Multi-channel LED structure is popularly implemented in some lighting systems such as indoor lighting and street lighting. Also, in display backlighting, advanced color-mixing and dimming LED systems the multi-channel LED driver solutions are used [62]. The multi-channel LED topologies connected to the line grid are usually composed of traditional five stages: the EMI filter, the bridge rectifier PFC stage, front-end DC/DC stage and multi-channel post-current-regulator stage. In multiple outputs LED driver independent output current control can be necessary. The postcurrent regulator can be performed in a linear mode current regulator or switch-

A simplified block schematic of the multi-channel constant current LED driver is

In the isolated LED driver solutions, the Flyback converter is widely used in multiple-output Flyback LED driver to integrate DC-DC converter with PFC circuit. The constant current source of multiple channel LED can be supplied in linear mode as shown in **Figure 20b** or with switch-mode converter as depicted in **Figure 20c** [63]. In **Figure 20c** the current source for the LED string is achieved by

In multi-channel applications there are also non-isolated LED driver circuits application. In this kind of LED driver, the single-inductor multiple-output (SIMO) structure is more attractive [64]. It is based on several Buck converters arrangement. In the SIMO solution LED strings current are regulated by switching Bucktype power converters. Furthermore, a main Buck converter is used to interface the rectified voltage performing the PFC functions [65]. The inductor of the main Buck converter is shared with the multi-channel Buck regulators. The simplified schematic of the SIMO structure is shown in **Figure 21**. The noticeable advantage of the SIMO technologies is their compact size the low cost and high-power efficiency

a synchronous Buck current regulator to reduce the power losses.

resonant tank features a voltage gain lower than unity.

*DOI: http://dx.doi.org/10.5772/intechopen.97098*

*Passive and Active Topologies Investigation for LED Driver Circuits*

output power is obtained by reducing the frequency and vice versa.

MOSFETs driven in synchronous mode by a suitable control technique [61].

**4.6 Multiple outputs LED driver circuits**

especially at the increasing of LED strings.

mode converter.

**83**

reported in **Figure 20a**.

A lower resonant frequency *f*r2 appears at light load operation. In this operative condition, LM must be considered. The resonant frequency consequently changes.

$$f\_{r2} = \frac{1}{2\pi \bullet \sqrt{(\mathbf{L\_R} + \mathbf{L\_M}) \bullet \mathbf{C\_R}}} \tag{43}$$

From (42) and (43) appears that *fr*<sup>1</sup> > *fr*2. The frequency *fr*<sup>2</sup> is also called the second resonance frequency. The LLC converter can operate in several ways related to the input voltage and load current conditions. The difference between the two resonant frequencies depends on the relationship between LM and LR. Usually, the LLC converter operates at a constant duty cycle. The condition *fsw* < *fr*<sup>2</sup> is not used in actual applications because an instability condition arises from the study of the transfer function of the converter [56]. In LLC converter there are three different operative conditions: *fr*<sup>2</sup> *> fsw* > *fr*1*, fsw* = *fr*<sup>1</sup> and*, fsw* > *fr*1. Referring to the LLC converter shown in **Figure 19a**, the resonant converter waveforms in the three operation modes are shown in **Figure 19b**.

At resonant frequency operation, at *f*sw = *f*r1, the resonant tank has unity gain and the best efficiency is reached. Primary-side and secondary-side RMS currents are the lowest values. In the primary-side switches, ZVS operation is achieved while on the secondary-side the diodes operate in zero current switching (ZCS). Furthermore, In the narrow neighborhood of *f*R1 the gain does not depend on the load conditions [57]. The analysis of the gain behavior depending on the electrical parameters of the resonant tank and load request. A detailed analysis is reported in [58].

At the *f*sw above *f*r1, the switching period is shorter than the resonant period. The resonant half cycle is not fully completed by the starting of the other half of the switching cycle, as shown in **Figure 19b**. In this case, on the secondary side, the rectifier diodes do not achieve the ZCS operating in hard switching. Also in this

#### **Figure 19.**

*(a) LLC converter schematic. (b) Main converter waveforms at fr2 > fsw > fr1, fsw = fr1 and, fsw > fr1. (c) Simplified current mode controller with VCO.*

#### *Passive and Active Topologies Investigation for LED Driver Circuits DOI: http://dx.doi.org/10.5772/intechopen.97098*

frequency *f*R1 occurs considering the higher load conditions. In this case the LM can

2π ∙ ffiffiffiffiffiffiffiffiffiffiffiffiffiffi LR ∙CR

2π ∙ ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ð Þ LR þ LM ∙CR

From (42) and (43) appears that *fr*<sup>1</sup> > *fr*2. The frequency *fr*<sup>2</sup> is also called the second resonance frequency. The LLC converter can operate in several ways related to the input voltage and load current conditions. The difference between the two resonant frequencies depends on the relationship between LM and LR. Usually, the LLC converter operates at a constant duty cycle. The condition *fsw* < *fr*<sup>2</sup> is not used in actual applications because an instability condition arises from the study of the transfer function of the converter [56]. In LLC converter there are three different operative conditions: *fr*<sup>2</sup> *> fsw* > *fr*1*, fsw* = *fr*<sup>1</sup> and*, fsw* > *fr*1. Referring to the LLC converter shown in **Figure 19a**, the resonant converter waveforms in the three

At resonant frequency operation, at *f*sw = *f*r1, the resonant tank has unity gain and the best efficiency is reached. Primary-side and secondary-side RMS currents are the lowest values. In the primary-side switches, ZVS operation is achieved while on the secondary-side the diodes operate in zero current switching (ZCS). Furthermore, In the narrow neighborhood of *f*R1 the gain does not depend on the load conditions [57]. The analysis of the gain behavior depending on the electrical parameters of the

At the *f*sw above *f*r1, the switching period is shorter than the resonant period. The resonant half cycle is not fully completed by the starting of the other half of the switching cycle, as shown in **Figure 19b**. In this case, on the secondary side, the rectifier diodes do not achieve the ZCS operating in hard switching. Also in this

resonant tank and load request. A detailed analysis is reported in [58].

*(a) LLC converter schematic. (b) Main converter waveforms at fr2 > fsw > fr1, fsw = fr1 and, fsw > fr1.*

A lower resonant frequency *f*r2 appears at light load operation. In this operative condition, LM must be considered. The resonant frequency consequently changes.

p (42)

<sup>p</sup> (43)

*fr*<sup>1</sup> <sup>¼</sup> <sup>1</sup>

*Light-Emitting Diodes and Photodetectors - Advances and Future Directions*

*fr*<sup>2</sup> <sup>¼</sup> <sup>1</sup>

be neglected and *f*R1 is given by

operation modes are shown in **Figure 19b**.

**Figure 19.**

**82**

*(c) Simplified current mode controller with VCO.*

operative condition, on the primary-side switches, the ZVS is reached. Finally, the resonant tank features a voltage gain lower than unity.

In the switching frequency between the two resonant frequencies (*f*r2 > *f*sw > *f*r1). The resonant tank gives a voltage gain higher than unity. The primary-side switches commutate in ZVS and in the secondary-side diodes achieve ZCS. In this operative condition, the peak value of the resonant current circulating through the LM is larger leading to higher conduction losses through the converter. Based on the load the equivalent impedance connected to the half-bridge switching leg can be either inductive or capacitive at frequency variation. Usually, the LLC converter operates in the region where the input impedance of the resonant tank has an inductive behavior (i.e. it increases with *f*sw) [59]. Furthermore, the ZVS mode on the primary-side is achieved only if the tank input impedance Zir is inductive. This operative condition can be controlled by changing the switching frequency. Higher output power is obtained by reducing the frequency and vice versa.

In the LED driver application, the output current must be controlled. In LLC the current mode controller is arranged with a voltage-controlled oscillator (VCO) that change the current control signal in variable switching frequency to drive the primary-side MOSFETs [60]. A simplified schematic of the current control with the VCO block is depicted in **Figure 19c**. The drawback of the LLC converter results from the difficulty in achieving consistent dynamic performance over wide-operating conditions. To reduce the switching losses on the secondary-side a synchronous rectifier solution may be arranged. In this case the diodes are replaced by low voltage MOSFETs driven in synchronous mode by a suitable control technique [61].

## **4.6 Multiple outputs LED driver circuits**

Multi-channel LED structure is popularly implemented in some lighting systems such as indoor lighting and street lighting. Also, in display backlighting, advanced color-mixing and dimming LED systems the multi-channel LED driver solutions are used [62]. The multi-channel LED topologies connected to the line grid are usually composed of traditional five stages: the EMI filter, the bridge rectifier PFC stage, front-end DC/DC stage and multi-channel post-current-regulator stage. In multiple outputs LED driver independent output current control can be necessary. The postcurrent regulator can be performed in a linear mode current regulator or switchmode converter.

A simplified block schematic of the multi-channel constant current LED driver is reported in **Figure 20a**.

In the isolated LED driver solutions, the Flyback converter is widely used in multiple-output Flyback LED driver to integrate DC-DC converter with PFC circuit. The constant current source of multiple channel LED can be supplied in linear mode as shown in **Figure 20b** or with switch-mode converter as depicted in **Figure 20c** [63]. In **Figure 20c** the current source for the LED string is achieved by a synchronous Buck current regulator to reduce the power losses.

In multi-channel applications there are also non-isolated LED driver circuits application. In this kind of LED driver, the single-inductor multiple-output (SIMO) structure is more attractive [64]. It is based on several Buck converters arrangement. In the SIMO solution LED strings current are regulated by switching Bucktype power converters. Furthermore, a main Buck converter is used to interface the rectified voltage performing the PFC functions [65]. The inductor of the main Buck converter is shared with the multi-channel Buck regulators. The simplified schematic of the SIMO structure is shown in **Figure 21**. The noticeable advantage of the SIMO technologies is their compact size the low cost and high-power efficiency especially at the increasing of LED strings.

#### *Light-Emitting Diodes and Photodetectors - Advances and Future Directions*

discussed. The main current control strategies are described, and the dimming features are also considered. Furthermore, the power converters connected to the AC line are explored considering the one-stage and two-stage converter solutions. In the one-stage LED driver a Flyback converter description is focused. The design issues and the control method to meet the output current regulation and the highpower factor request are explored. Afterwards, the two-stage driver converters for higher power applications are investigated. The first stage Boost converter PFC circuit design and control issues are exanimated, and the interleaved solution is introduced. The second stage LLC for a higher current LED driver is also considered providing basic information on the operation and the applications. Finally, multichannel LED driver circuits in non-isolated and isolated conditions are presented

*Passive and Active Topologies Investigation for LED Driver Circuits*

*DOI: http://dx.doi.org/10.5772/intechopen.97098*

and discussed.

**Author details**

**85**

Salvatore Musumeci

Department of Energy "G. Ferraris", Politecnico di Torino, Torino, Italy

© 2021 The Author(s). Licensee IntechOpen. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/ by/3.0), which permits unrestricted use, distribution, and reproduction in any medium,

\*Address all correspondence to: salvatore.musumeci@polito.it

provided the original work is properly cited.

#### **Figure 20.**

*Multi-channel LED driver circuits (a) block scheme of general AC LED driver system for multi-channel LED string. (b) Flyback converter solution with linear regulator on the secondary side. (c) Flyback converter solution with switching type synchronous Buck current regulator.*

**Figure 21.** *Multi-channel LED driver circuits with single-inductor multiple-output solution.*

For high current LED string the LLC converter with multiple-output secondary of the HF transformer can be considered [66]. In the secondary side as described in **Figure 20b** and **Figure 20c** a switching or linear type current regulator is added to drive the LED strings.

#### **5. Conclusion**

The LED driver circuits in several applications needs are investigated. The passive and active circuits are critically evaluated in terms of power request, topology simplicity, efficiency, reliability, and cost. The LED driver circuits are evaluated based on the different supply sources and power request. The DC-DC converters connected directly to a DC source such as battery are classified and pro and cons are

## *Passive and Active Topologies Investigation for LED Driver Circuits DOI: http://dx.doi.org/10.5772/intechopen.97098*

discussed. The main current control strategies are described, and the dimming features are also considered. Furthermore, the power converters connected to the AC line are explored considering the one-stage and two-stage converter solutions. In the one-stage LED driver a Flyback converter description is focused. The design issues and the control method to meet the output current regulation and the highpower factor request are explored. Afterwards, the two-stage driver converters for higher power applications are investigated. The first stage Boost converter PFC circuit design and control issues are exanimated, and the interleaved solution is introduced. The second stage LLC for a higher current LED driver is also considered providing basic information on the operation and the applications. Finally, multichannel LED driver circuits in non-isolated and isolated conditions are presented and discussed.
