**5. SystemC and transaction level modelling**

This work uses SystemC and the TLM 2.0 as modelling and simulation tools, so in this section they will be described.

functionality and, as the model gets refined, those initial high-level modules are further divided into more specific interconnected modules, until the RTL is

*System Level Design and Conception of a System-on-a-Chip (SoC) for Cognitive Robotics*

In hardware models of higher levels of abstraction, executing all modules at each time step may produce an unnecessary overhead. Thinking of a digital systems as components connected by a bus, reading from and writing to it, it would be more efficient to execute modules only when they have something massages to send/ receive. This is the rationale behind Transaction Level Modelling (TLM), the mes-

With SystemC, an implementation of the TLM called TLM 2.0 is provided. It inherits all the SystemC capabilities, mainly the module concept, extending it with

reached [14].

**Figure 4.**

**Figure 5.**

**95**

*TLM basic elements [15].*

*Typical SystemC RTL module [14].*

**5.2 Transaction level modelling**

*DOI: http://dx.doi.org/10.5772/intechopen.98643*

sage exchange being called a transaction [15].

sockets, transactions and payloads (**Figure 5**).
