**7. Results**

### **7.1 Problem domain and simulation environment**

The experiments were performed using the Webots R2021a robotics simulator. In the context of the CAA, the reactive level of the agent was

**Figure 7.** *Simulation environment for start state.*

*System Level Design and Conception of a System-on-a-Chip (SoC) for Cognitive Robotics DOI: http://dx.doi.org/10.5772/intechopen.98643*

implemented inside this simulator, in the form of behaviours and controllers the interface with the environment. In the simulator, the planning problem domain was constructed: a simplified version of the blocks domain. The simulation consisted of three coloured boxes (red, green and blue) disposed in a given order around KUKA Youbot robot, which is a mobile robot with a robotic arm and a plate. The simulation environment and the robot in the initial state are shown in the **Figure 7**.

The planning problem consisted of reordering the blocks from the initial position shown in **Figure 7** so that the red block is in the left side or the arm, the blue in the right and the green in the front.

**Figure 8.** *Sequence diagram for graph expansion.*

**6. Proposed architecture**

*Robotics Software Design and Engineering*

**7. Results**

**Figure 7.**

**96**

*Simulation environment for start state.*

*TLM model of the SoC.*

**Figure 6.**

base and an auxiliary stage for test execution.

network are performed separately in the Join Node Module.

**7.1 Problem domain and simulation environment**

The experiments were performed using the Webots R2021a robotics simulator. In the context of the CAA, the reactive level of the agent was

The hardware architecture proposed in this work takes full advantage of SystemC and TLM 2.0 capability of developing executable specifications from system level to RTL. In this sense, the approach employed was to obtain a high level model and validate its functionality using experiments in a robotics context.

The TLM model proposed is shown in **Figure 6**. It consists of modified SystemC model of the *Rete* processor presented in the authors previous work [10]. As can be seen in **Figure 6**, the instinctive module now implements a detailed *Rete* processor, that uses two Content Addressable Memories (CAMs) to implement the knowledge

The Instruction Set Architecture (ISA) of the *Rete* processor described in [10] is still employed in this model, but now some tasks related to join node in the Rete
