**5.2 Transaction level modelling**

**5. SystemC and transaction level modelling**

shows the typical design flow for SystemC projects [14].

in this section they will be described.

*Robotics Software Design and Engineering*

**5.1 SystemC**

**Figure 3.**

**94**

*SystemC hardware design flow [14].*

This work uses SystemC and the TLM 2.0 as modelling and simulation tools, so

In the design of complex digital systems, obtaining a high-level executable specification of the project in early stages of the design process is useful for

detecting errors or validate functionality prior to implementation. This is one of the main advantages of SystemC, a C++ class library for hardware design at various abstraction levels - from system level to Register Transfer Level (RTL). **Figure 3**

The SystemC library contains elements that facilitates representation of hardware systems parallelism. Hardware models in SystemC are represented by modules that may run in parallel interconnected by ports and channels (**Figure 4**). In this way, the initial model may contain a few modules representing system level

In hardware models of higher levels of abstraction, executing all modules at each time step may produce an unnecessary overhead. Thinking of a digital systems as components connected by a bus, reading from and writing to it, it would be more efficient to execute modules only when they have something massages to send/ receive. This is the rationale behind Transaction Level Modelling (TLM), the message exchange being called a transaction [15].

With SystemC, an implementation of the TLM called TLM 2.0 is provided. It inherits all the SystemC capabilities, mainly the module concept, extending it with sockets, transactions and payloads (**Figure 5**).

**Figure 4.**

*Typical SystemC RTL module [14].*

**Figure 5.** *TLM basic elements [15].*
