**3.3 Multiplexer and demultiplexer**

The most important form of a combinational circuit and which is widely used in the field of communication is *Multiplexer and Demultiplexer Circuits.* The multiplexer circuit is used to transfer large number of channels carrying information to a smaller number of channels. Such circuit used to transmit digital data or binary information is called as *data selector or digital multiplexer.* In this data selector, the input line is selected according to the combination of select lines, suppose if there exists *2<sup>n</sup>* input line then the number of select line is *n* and there will be *only one* output line. For example in a 4x1 multiplexer, the number of input lines is 4 (*22 )* which shows there exists of *2* select lines. In these multiplexer circuits the inputs are named as *I0, I1, I2 and I3* and the two select lines are named as *S0* and *S1*. **Table 5** shows the various combinations of select line and corresponding input line is selected and obtained as output Y [4]. The boolean expression for the output Y is given below. **Figure 6** shows the Front panel and Block Diagram of 4x1 multiplexer. This design can be extended for higher versions like 8x1 and 16x1 types of multiplexer.

*Digital System Design DOI: http://dx.doi.org/10.5772/intechopen.97611*


#### **Table 5.** *Truth Table – 4\*1 Multiplexer.*

**Figure 6.** *Logic Diagram – 4\*1 Multiplexer.*

**Figure 5** shows the design and implementation of full subtractor circuit in LabVIEW environment, where the front panel that two inputs Input A, Input B, and Input Bin, the outputs are Difference D and Borrow Ouptut. The block diagram in LabVIEW environment shows the logic gate implementation for the above

*Input Variables Output Variables*

*LabVIEW - A Flexible Environment for Modeling and Daily Laboratory Use*

**A B** *B*in **Difference D Borrow B** 0 00 0 0 0 01 1 1 0 10 1 1 0 11 0 1 1 00 1 0 1 01 0 0 1 10 0 0 1 11 1 1

The most important form of a combinational circuit and which is widely used in the field of communication is *Multiplexer and Demultiplexer Circuits.* The multiplexer circuit is used to transfer large number of channels carrying information to a smaller number of channels. Such circuit used to transmit digital data or binary information is called as *data selector or digital multiplexer.* In this data selector, the input line is selected according to the combination of select lines, suppose if there exists *2<sup>n</sup>* input line then the number of select line is *n* and there will be *only one* output line. For example in a 4x1 multiplexer, the number of input lines is 4 (*22*

which shows there exists of *2* select lines. In these multiplexer circuits the inputs are named as *I0, I1, I2 and I3* and the two select lines are named as *S0* and *S1*. **Table 5** shows the various combinations of select line and corresponding input line is selected and obtained as output Y [4]. The boolean expression for the output Y is given below. **Figure 6** shows the Front panel and Block Diagram of 4x1 multiplexer.

This design can be extended for higher versions like 8x1 and 16x1 types of

*)*

obtained expression.

*Logic Diagram – Full Subtractor.*

**Table 4.**

**Figure 5.**

*Truth Table – Full Subtractor.*

multiplexer.

**162**

**3.3 Multiplexer and demultiplexer**

The Boolean expressions are

$$Output\ Y = \overline{\mathcal{S}\_0 \mathcal{S}\_1} I\_0 + \overline{\mathcal{S}\_0} \mathcal{S}\_1 I\_1 + \mathcal{S}\_0 \overline{\mathcal{S}\_1} I\_2 + \mathcal{S}\_0 \mathcal{S}\_1 I\_3 \tag{9}$$

The term demultiplex is just a opposite way of multiplexer, here in this combinational circuit there are one input channel and distributes the data over several channels. Therefore if the number of input channel is *1* then the number of output will be 2n output channels. The combination of select lines control the output channel through which the input data must be transmitted. **Table 6** gives the truth table for 1-to-8 demultiplexer, the front panel and block diagram for 1-to-8 demultiplexer is shown in **Figure 7**.

The selection input line S0, S1, S2 are activated according to the bit combination for each output as given in Eq. (10) to Eq. (17). For instance, if the selection input combination is 010, the input *I* is transmitted to Y2. The Boolean expressions for each output line is given below

$$Y\mathbf{O} = \overline{\mathbf{S\_2S\_1S\_0}}I\tag{10}$$

$$Y\mathbf{1} = \overline{\mathbf{S\_2S\_1}}\mathbf{S\_0}I\tag{11}$$

$$Y\mathfrak{Z} = \overline{\mathfrak{S}\_2} \mathfrak{S}\_1 \overline{\mathfrak{S}\_0} I \tag{12}$$

$$Y\mathfrak{B} = \overline{\mathfrak{S}\_2} \mathbf{S}\_1 \mathbf{S}\_1 I \tag{13}$$

$$Y4 = \mathbb{S}\_2 \overline{\mathbb{S}\_1} \overline{\mathbb{S}\_0} I \tag{14}$$


#### **Table 6.** *Truth Table – 1\*8 Demultiplexer.*

**Figure 7.** *Logic Diagram – 1\*8 Demultiplexer.*


$$Y\mathfrak{G} = \mathbb{S}\_2\mathbb{S}\_1\overline{\mathfrak{S}\_0}I \tag{16}$$

$$Y\nabla = \mathbf{S\_2S\_1S\_0}I\tag{17}$$

output 4-bit gray is defined as G0, G2, G3, and G4 as shown in **Figure 8**. The corresponding boolean expression for binary to gray code conversion is given below

**B0 B1 B2 B3 G0 G1 G2 G3** 0 0000 00 0 0 001 0 00 1 0 010001 1 0 011001 0 0 1000 1 1 0 0 1010 1 1 1 0 1100 10 1 0 1110100 1 000 1 1 0 0 1 001 1 1 0 1 1 0101 1 1 1 1 011 1 1 1 0 1 100 1 0 1 0 1 101 1 0 1 1 1 1101 00 1 1 111 1000

Gray code is also called as Reflected Binary Code (RBC), Reflected Binary (RB) or Gray code, Cyclic Code, is defined as an ordering of the binary number system

*3.4.2 Gray to binary code converters*

*Logic Diagram – Binary to Gray Code Converter.*

**Table 7.**

*Digital System Design*

*DOI: http://dx.doi.org/10.5772/intechopen.97611*

**Figure 8.**

**165**

*Truth Table – Binary to Gray Converter.*

*G*<sup>0</sup> ¼ *B*<sup>0</sup> (18) *G*<sup>1</sup> ¼ *B*<sup>0</sup> ⨁*B*<sup>1</sup> (19) *G*<sup>2</sup> ¼ *B*<sup>2</sup> ⨁*B*<sup>1</sup> (20) *G*<sup>3</sup> ¼ *B*<sup>3</sup> ⨁*B*<sup>2</sup> (21)
