*(i) Design of half-adders*

A half adder is a combination logic circuit that uses two inputs (A and B) and two outputs (Sum S and Carry C). **Table 1** shows the truth table the various combinations of inputs and its corresponding outputs. The output Sum S and Carry C is obtained and the k-map is used to get the logical equation. The Boolean expressions are

$$\text{Sum S} = A \oplus B \tag{1}$$

$$\text{Carry } \mathbf{C} = \mathbf{A}\mathbf{B} \tag{2}$$

**Figure 2** shows the design and implementation of half adder circuit in LabVIEW environment, where the front panel that two inputs Input A and Input B, the outputs are Sum and Carry [3]. The block diagram in LabVIEW environment shows the logic gate implementation for the above obtained expression.
