**Table 4.**

#### **Figure 5.** *Logic Diagram – Full Subtractor.*

**Figure 5** shows the design and implementation of full subtractor circuit in LabVIEW environment, where the front panel that two inputs Input A, Input B, and Input Bin, the outputs are Difference D and Borrow Ouptut. The block diagram in LabVIEW environment shows the logic gate implementation for the above obtained expression.

The Boolean expressions are

*Logic Diagram – 4\*1 Multiplexer.*

**Table 5.**

**Figure 6.**

**163**

*Truth Table – 4\*1 Multiplexer.*

*Digital System Design*

*DOI: http://dx.doi.org/10.5772/intechopen.97611*

tiplexer is shown in **Figure 7**.

each output line is given below

*Output Y* ¼ *S*0*S*1*I*<sup>0</sup> þ *S*0*S*1*I*<sup>1</sup> þ *S*0*S*1*I*<sup>2</sup> þ *S*0*S*1*I*<sup>3</sup> (9)

*Y*0 ¼ *S*2*S*1*S*0*I* (10) *Y*1 ¼ *S*2*S*1*S*0*I* (11) *Y*2 ¼ *S*2*S*1*S*0*I* (12) *Y*3 ¼ *S*2*S*1*S*1*I* (13) *Y*4 ¼ *S*2*S*1*S*0*I* (14)

The term demultiplex is just a opposite way of multiplexer, here in this combinational circuit there are one input channel and distributes the data over several channels. Therefore if the number of input channel is *1* then the number of output will be 2n output channels. The combination of select lines control the output channel through which the input data must be transmitted. **Table 6** gives the truth table for 1-to-8 demultiplexer, the front panel and block diagram for 1-to-8 demul-

*Selection Inputs Input Channels Output S1 S0 I0 I1 I2 I3 Y* 0 0 0XXX 0 0 0 1 XXX 1 0 1 X0XX 0 0 1 X 1XX 1 1 0 0X0X 0 1 0 1X1X 1 1 1 0XX0 0 1 1 1 XX 1 1

The selection input line S0, S1, S2 are activated according to the bit combination for each output as given in Eq. (10) to Eq. (17). For instance, if the selection input combination is 010, the input *I* is transmitted to Y2. The Boolean expressions for
