**2.1 Micro thermal device architecture**

Small dimensions (nanometers to micrometers) are appropriate in the sensitive

Sensing requires energy. A certain provision of energy autonomy is needed for sensors to be deployed in remote locations, harsh environments, or where they need to remain temporary unattended. Batteries is a common way to provide such autonomy, but their charge is finite impeding long-term autonomy scenarios. Moreover, their recharge, replacement and disposal imply a logistic and environmental burden that will not be affordable when IoT gets to its full extent mobilizing

Secondary batteries can be kept recharged by coupling them with energy harvesters able to draw energy present in the environment [5]. Heat is abundant in natural scenarios, and waste heat is also abundant in human-made scenarios due to laws of thermodynamics and our profuse use of thermal machines. When such heat gives rise to temperature gradients (a situation as simple as a hot surface exposed to air), thermoelectricity is a convenient way to extract electric energy from them [6, 7]. For that extraction to be optimum, the external thermal gradient needs to be fully transposed into the thermoelectric generator itself. Physical interaction of small devices with their environment may exploit profitably some scale factors when going down in dimensions, but, sometimes, small sizes pose a handicap or challenge for such interaction, too. This is the case when trying to cool down locally a part of a small device by exchanging heat with the surrounding air. This chapter tries to illustrate this point by sharing the issues and strategies the authors have dealt, and are dealing with, in their quest for silicon-based miniaturized thermo-

Silicon technology has been developed around an enabling and highly abundant semiconductor material. It is a mature technology apt to mass-production of devices with economy of scale and it is the champion technology of miniaturization. Not surprisingly, it boosted microelectronics in the XX century and nanoelectronics in the XXI century. In addition to the set of techniques that allow the fabrication of integrated circuits by depositing and patterning thin films on a silicon wafer, silicon technologies also developed micromachining techniques that allow carving and shaping the silicon wafers into structures that are able to interact with the environment. Sensors and actuators belong to the latter category. Since energy harvesters are environmental interacting devices and, application-wise, they should not be much larger than the sensors they will feed, it is only logical that their fabrication will similarly benefit from the silicon technologies toolbox. These technologies do not only excel in miniaturization but also in *integration* capabilities. This is an important aspect as well. Traditional thermoelectric generators are *assembled* from couples of semiconductor pellets, various millimeters in side, that are arranged electrically in series and thermally in parallel together with additional connecting strips and appropriate thermal elements. When going down in dimensions, assembly becomes harder and offers much less latitude for process automation. In this way, resourcing to technologies that inherently offer integration capabilities

part of sensors when they need to interact with phenomena or entities equally characterized by such small dimensions (light, molecules, living cells … ). An overall small size for the sensors themselves is not devoid of interest either. The smaller they are, the more sustainable their fabrication is in terms of materials and energy, and the more cost-effective they become. Small size is also enabling in itself, e.g.

medical implants, as well as convenient, e.g. payloads.

*Heat Transfer - Design, Experimentation and Applications*

**2. Silicon-based thermoelectric generators**

electric generators.

is convenient, if not a must.

**350**

tens of billions of devices and an even larger number of sensors.

The traditional thermoelectric generators mentioned above feature a π-architecture, where the π symbol gives a visual clue about how each thermocouple is built assembling vertically two semiconductor pellets (*aka* legs) of different polarity (to add-up the contribution of both electrons and holes) and connecting them electrically with a horizontal conductive strip. Several of those thermocouples are then connected in 1D or 2D arrangements [8]. Such disposition is well adapted to exploit vertically occurring gradients: the bottom part is placed in contact with the heat source while the top part contacts the heat sink and the thermoelectric material in between translates the heat flowing through it (or the temperature difference spanning across it) into magnitudes of electrical relevance, *V* and *I*, and therefore power (*VI)*.

Silicon technologies are of planar nature. They enable massive parallelism at *x* and *y* directions for shaping *laterally* devices made from the superposition of several active thin films. Such shaping also involves patterning in the *z* direction, but the accumulated depth of the films is much lower than the lateral dimensions at play, leading to aspect ratios that are opposite to those that characterize π –shape thermocouples.

The main objective when defining the architecture and the technological route for a *micro* thermoelectric device is to obtain two areas of contrasted temperature in the *surface* of the chip since the thermoelectric materials will be arranged *laterally*. An architecture that translates an external vertical gradient into an internal lateral one is called *transversal,* and to make it possible a *thermal isolated platform* is defined.

The platform consists of a thin silicon area fabricated by eliminating the silicon beneath it. In order to preserve its thermal isolation from the surrounding bulk silicon, the physical connections between them should be minimized. Such connections are the mechanical supports that keep the platform in place (e.g. ancillary silicon bridges) and the thermoelectric materials themselves (and whatever supports they may need). In order to minimize the thermal conduction of these elements, they must be produced with *low thermal conductance eith*er by resourcing to low thermal *conductivity* materials, when available and technologically feasible, or by acting on their *geometrical dimensions* making them long and thin.

**Figure 1** shows the schematics for such a device. Any hot surface in which this device is placed will act as a heat source. The top surface will be exposed to air acting as heat sink and will exchange heat with it. Due to their different thermal mass, the bulk rim area will hardly cool down, thus being the hot part of the device, while the platform will experience a larger decrease of temperature becoming the cold(er) part of it.

With respect to the thermoelectric material, the depicted device follows a unileg approach. Two thermoelectric materials are still at play, but a metal one replaces one of the semiconductor legs in order to close the circuit. Some thermoelectric performance is sacrificed because metals behave poorly thermoelectrically (they have higher thermal conductivities and close to zero Seebeck coefficients), but for the architecture presented and to keep processing simple, the use of a metal leg is technologically convenient.

Regarding the semiconductor thermoelectric material, one distinct feature of our approach is resourcing to silicon materials, namely arrays of silicon nanowires (Si NWs). The rationale behind this option is to attempt the fabrication of *all-silicon* microgenerators, thus leveraging the full potential of silicon technologies. Thermoelectric performance of bulk silicon at ambient or moderate temperatures is bad because of its high thermal conductivity. Incidentally, this is the reason why it is

higher their thermal resistance is. This leads to a platform better isolated from the bulk silicon rim and a larger resulting temperature difference (ΔT). Growing longer nanowires requires longer processing times, so a clever way of obtaining arbitrarily long nanowires in a reasonable time is to divide the span to be bridged by them into a number of consecutive trenches (see **Figure 1**). We usually cover lateral voids of several tens of microns by dividing them into 10 or 15 μm wide trenches (as shown in the sketch of **Figure 1**). It must be noted that increasing the length of the NWs has a linear impact on their thermal conduction, but a sublinear impact on the overall thermal conductance of the device. NWs are just one of the several concurring heat leak paths across the platform and rim (metal legs, metal leg supports, platform mechanical supports, air itself), so increasing their length beyond the point where their thermal conductance starts competing with those of others makes no sense. Of course, another way to affect the thermal conduction of the thermoelectric material is choosing materials with lower thermal conductivity. In our case, and without moving beyond silicon compatible materials, SiGe NWs, which can be grown in a similar way, but exhibit better thermal properties, have been successfully integrated producing ΔTs significantly larger than Si NWs, specially under

natural convection and the absence of heat exchangers [17].

*Managing Heat Transfer Issues in Thermoelectric Microgenerators*

*DOI: http://dx.doi.org/10.5772/intechopen.96246*

larger power. Power (*P*) goes as *V*<sup>2</sup>

choices.

**353**

As said, longer NWs generally imply larger ΔT and, thus, a larger

thermovoltage. However, a resulting larger voltage is not necessarily associated to a

It must be noted that the heat transfer issues discussed in this chapter revolve

When considering the optimum design for a thermoelectric microgenerator (μTEG) the generated power is the parameter which needs to be maximized. It is well known that for a given μTEG with its own internal resistance, the power that is transferred to the load is maximized when the internal resistance and the load resistance are equal. This case is usually known as load matching condition [23].

about the challenge of exchanging heat in planar micromachined structures exhibiting very small exchange surfaces [18–22], while the particular nature of the thermoelectric material employed (e.g. NWs) is of no significance: the same conclusions will apply if silicon membranes, silicon-based thin films, or any other

thermoelectric films of interest were considered instead.

**2.2 Optimization considerations (load matching)**

will also increase the electrical resistance of the device, a trade-off is established. Beyond certain NW length, *V* may still increase but *P* will decrease. The value at which this happens will not only depend on the balance of the thermal and electrical properties of the thermoelectric material, but also on the thermal relevance of the thermoelectric material in the thermal design of the overall device. This is of particular significance for this chapter as the way the platform exchanges heat with the ambient is an important element of the thermal resistance of the whole device and determines the corresponding internal ΔT distribution. As commented, the goal of the thermal design of the device is to transpose most of the *external* gradient available to the active *internal* hot and cold areas. For that, the thermal resistance across platform and bulk silicon rim should be larger than the other two thermal resistances in series: the one of the hot part with the heat sink and the one of the cold part with the surrounding air. Being a solid–solid interface in usual application scenarios, keeping the former small poses no great problem; however, reducing the latter is much more challenging. As will be shown, the degree to which that reduction can be achieved would affect the tipping point of the thermal and electrical trade-off and impact also on materials and dimensional

/*R*, and since increasing the length of the NWs

**Figure 1.**

*From left to right and top to bottom: 3D sketch of an integrated planar micro-thermocouple; SEM image of a fabricated device; schematic cross-section of the device identifying the thermally isolated platform and other relevant elements, and the expected heat flow from hot to cold areas in a transversal architecture. The typical area for the platform of the devices discussed is 1 mm<sup>2</sup> .*

removed under the platform in the first place. However, nanostructuration of silicon in at least one dimension was shown to significantly lower its thermal conductivity when such spatial constraint is in the order or lower than the mean free paths of heat carriers (phonons) [9, 10].

Moreover, arrays of Si NWs can be conveniently grown as a post-process using a *bottom-up* method, known as CVD-VLS, which is mediated by previously deposited catalytic gold nanoparticles [11]. Following this procedure, this material can spontaneously fill the lateral void between the platform and the surrounding bulk silicon rim. Moreover, the NWs are attached quasi-epitaxially to the giving and receiving silicon walls minimizing any thermal and electrical contact resistance that could appear at those connection points [12]. Such minimization of parasitic resistances is an advantage of micro-*integration* when compared to macro-*assembly*. Further details on how Si NWs are grown and integrated in the proposed architecture can be found in our earlier published work [13–16].

The metal leg cannot be integrated in the same self-standing way. It is deposited as a thin film, so it needs a physical support. These ancillary supports need to be thermally optimized since they bridge the hot and cold areas. The nature of these supports has evolved across the different generations of our devices: from long and thin silicon bridges (400 μm x 100 μm x 15 μm) to wide and very thin Si3N4 membranes (100 μm x 1000 μm x 0.3 μm). Since thermal conductivity of Si3N4 is two orders of magnitude lower than the one of silicon, there is a net gain in thermal conductance, while enabling a shorter and wider (and less electrically resistive) metal leg.

The thermal impact on platform isolation of the *active* thermoelectric material, Si NWs, can be modulated by the nanowire length. The longer the nanowires are, the

#### *Managing Heat Transfer Issues in Thermoelectric Microgenerators DOI: http://dx.doi.org/10.5772/intechopen.96246*

higher their thermal resistance is. This leads to a platform better isolated from the bulk silicon rim and a larger resulting temperature difference (ΔT). Growing longer nanowires requires longer processing times, so a clever way of obtaining arbitrarily long nanowires in a reasonable time is to divide the span to be bridged by them into a number of consecutive trenches (see **Figure 1**). We usually cover lateral voids of several tens of microns by dividing them into 10 or 15 μm wide trenches (as shown in the sketch of **Figure 1**). It must be noted that increasing the length of the NWs has a linear impact on their thermal conduction, but a sublinear impact on the overall thermal conductance of the device. NWs are just one of the several concurring heat leak paths across the platform and rim (metal legs, metal leg supports, platform mechanical supports, air itself), so increasing their length beyond the point where their thermal conductance starts competing with those of others makes no sense. Of course, another way to affect the thermal conduction of the thermoelectric material is choosing materials with lower thermal conductivity. In our case, and without moving beyond silicon compatible materials, SiGe NWs, which can be grown in a similar way, but exhibit better thermal properties, have been successfully integrated producing ΔTs significantly larger than Si NWs, specially under natural convection and the absence of heat exchangers [17].

As said, longer NWs generally imply larger ΔT and, thus, a larger thermovoltage. However, a resulting larger voltage is not necessarily associated to a larger power. Power (*P*) goes as *V*<sup>2</sup> /*R*, and since increasing the length of the NWs will also increase the electrical resistance of the device, a trade-off is established. Beyond certain NW length, *V* may still increase but *P* will decrease. The value at which this happens will not only depend on the balance of the thermal and electrical properties of the thermoelectric material, but also on the thermal relevance of the thermoelectric material in the thermal design of the overall device. This is of particular significance for this chapter as the way the platform exchanges heat with the ambient is an important element of the thermal resistance of the whole device and determines the corresponding internal ΔT distribution. As commented, the goal of the thermal design of the device is to transpose most of the *external* gradient available to the active *internal* hot and cold areas. For that, the thermal resistance across platform and bulk silicon rim should be larger than the other two thermal resistances in series: the one of the hot part with the heat sink and the one of the cold part with the surrounding air. Being a solid–solid interface in usual application scenarios, keeping the former small poses no great problem; however, reducing the latter is much more challenging. As will be shown, the degree to which that reduction can be achieved would affect the tipping point of the thermal and electrical trade-off and impact also on materials and dimensional choices.

It must be noted that the heat transfer issues discussed in this chapter revolve about the challenge of exchanging heat in planar micromachined structures exhibiting very small exchange surfaces [18–22], while the particular nature of the thermoelectric material employed (e.g. NWs) is of no significance: the same conclusions will apply if silicon membranes, silicon-based thin films, or any other thermoelectric films of interest were considered instead.

## **2.2 Optimization considerations (load matching)**

When considering the optimum design for a thermoelectric microgenerator (μTEG) the generated power is the parameter which needs to be maximized. It is well known that for a given μTEG with its own internal resistance, the power that is transferred to the load is maximized when the internal resistance and the load resistance are equal. This case is usually known as load matching condition [23].

removed under the platform in the first place. However, nanostructuration of silicon in at least one dimension was shown to significantly lower its thermal conductivity when such spatial constraint is in the order or lower than the mean

*From left to right and top to bottom: 3D sketch of an integrated planar micro-thermocouple; SEM image of a fabricated device; schematic cross-section of the device identifying the thermally isolated platform and other relevant elements, and the expected heat flow from hot to cold areas in a transversal architecture. The typical*

*.*

Moreover, arrays of Si NWs can be conveniently grown as a post-process using a *bottom-up* method, known as CVD-VLS, which is mediated by previously deposited catalytic gold nanoparticles [11]. Following this procedure, this material can spontaneously fill the lateral void between the platform and the surrounding bulk silicon rim. Moreover, the NWs are attached quasi-epitaxially to the giving and receiving silicon walls minimizing any thermal and electrical contact resistance that could appear at those connection points [12]. Such minimization of parasitic resistances is an advantage of micro-*integration* when compared to macro-*assembly*. Further details on how Si NWs are grown and integrated in the proposed architecture can be

The metal leg cannot be integrated in the same self-standing way. It is deposited as a thin film, so it needs a physical support. These ancillary supports need to be thermally optimized since they bridge the hot and cold areas. The nature of these supports has evolved across the different generations of our devices: from long and thin silicon bridges (400 μm x 100 μm x 15 μm) to wide and very thin Si3N4 membranes (100 μm x 1000 μm x 0.3 μm). Since thermal conductivity of Si3N4 is two orders of magnitude lower than the one of silicon, there is a net gain in thermal conductance, while enabling a shorter and wider (and less electrically resistive)

The thermal impact on platform isolation of the *active* thermoelectric material, Si NWs, can be modulated by the nanowire length. The longer the nanowires are, the

free paths of heat carriers (phonons) [9, 10].

*area for the platform of the devices discussed is 1 mm<sup>2</sup>*

*Heat Transfer - Design, Experimentation and Applications*

found in our earlier published work [13–16].

metal leg.

**352**

**Figure 1.**

Considering the electrical circuit diagram shown in **Figure 2**, which represents a μTEG, formed by a voltage source (VOC) and its internal electrical resistance (RTEG), connected to a load resistance (RL), it is straightforward to evaluate the total dissipated power at the load as:

$$P\_L = V\_L \cdot I\_L = I\_L^2 \cdot R\_L = \left(\frac{V\_{oc}}{R\_{TEG} + R\_L}\right)^2 \cdot R\_L \tag{1}$$

Finding the value of RL which maximizes PL implies after a few calculations the load matching condition, RTEG = RL. It is important to notice that the only parameter allowed to change in this optimization is the load resistance. Therefore, one can write the maximum power as:

$$P\_{L,max} = \frac{V\_{oc}^2}{4R\_L} = \frac{V\_{oc}^2}{4R\_{TEG}}\tag{2}$$

*PL*, *max* <sup>¼</sup> *<sup>V</sup>*<sup>2</sup>

Δ*T* ¼ *ΔTA*

the μTEG, or Thot-Tcold from **Figure 4**. Therefore:

*Power output of a μTEG versus load resistance for different RTEG values.*

*Managing Heat Transfer Issues in Thermoelectric Microgenerators*

*DOI: http://dx.doi.org/10.5772/intechopen.96246*

conductance to the ambient.

**Figure 3.**

**Figure 4.**

**355**

*oc* 4*RTEG*

*Simplified thermal conductance network describing the μTEG with parallel and series thermal conductances.*

Where *S* is the Seebeck coefficient and ΔT is the temperature difference across

Where ΔTA is the total available temperature difference, Tamb-Thot. KTEG is the internal thermal conductance of the μTEG and KS represents the thermal

important to keep in mind that KTEG is bound to increase, as they are inversely proportional. This is because of the implicit assumption that changing KTEG implies a geometry modification, not a material property change and the geometry change affects both electrical resistance and thermal conductance of the μTEG. Ignoring any leakage contribution (KLK = 0 W/K) in Eq. (4), the power output (solid) and ΔT

When decreasing RTEG, as deemed appropriated in the previous paragraphs, it is

<sup>¼</sup> ð Þ *<sup>S</sup>* � <sup>Δ</sup>*<sup>T</sup>* <sup>2</sup> 4*RTEG*

*KS* ð Þ *KTEG* þ *KLK* þ *KS* (3)

(4)

As can be seen in **Figure 3**, where the output power of a μTEG is plotted versus load resistance for three different internal resistances, each curve has a maximum for the load matching condition. But now the influence of the internal resistance is highlighted, where the lower its value, the greater the power output. In **Figure 3**, for example, halving the internal resistance can double the power output at the load matching condition. This highlights the importance of reducing the internal resistance when designing a μTEG.

Some publications discussing load matching focus on the need to modify the internal resistance, increasing it, in order to match the load resistance [22]. According to **Figure 3**, this is in fact an error. It is always a better approach to minimize the internal resistance in order to increase the power output even further. Once the internal resistance is the minimum possible, then the load matching condition can be applied to maximize the power output. Actually, many integrated circuits exist which efficiently implement maximum power point tracking (MPPT) algorithms to extract the maximum power from a power source by modifying its load resistance.

This load matching approach can be analogously applied to the temperatures involved in the μTEG and is known as thermal matching. A simplified conductance network describing the μTEG (KTEG) in parallel with KLK accounting for parasitic thermal leakages and in series with KS representing the conductance to ambient (to both heat source and heat sink) is shown in **Figure 4**.

To explore which is the KTEG value that maximizes Pmax, as was done in the electrical case, Eq. (2) can be rewritten as:

#### **Figure 2.**

*Equivalent circuit of a μTEG, formed by a voltage source (VOC) and its internal resistance (RTEG), connected in series with a load resistance (RL).*

*Managing Heat Transfer Issues in Thermoelectric Microgenerators DOI: http://dx.doi.org/10.5772/intechopen.96246*

Considering the electrical circuit diagram shown in **Figure 2**, which represents a

*<sup>L</sup>* � *RL* <sup>¼</sup> *Voc*

Finding the value of RL which maximizes PL implies after a few calculations the load matching condition, RTEG = RL. It is important to notice that the only parameter allowed to change in this optimization is the load resistance. Therefore, one can

> *oc* 4*RL*

As can be seen in **Figure 3**, where the output power of a μTEG is plotted versus load resistance for three different internal resistances, each curve has a maximum for the load matching condition. But now the influence of the internal resistance is highlighted, where the lower its value, the greater the power output. In **Figure 3**, for example, halving the internal resistance can double the power output at the load matching condition. This highlights the importance of reducing the internal resis-

Some publications discussing load matching focus on the need to modify the

This load matching approach can be analogously applied to the temperatures involved in the μTEG and is known as thermal matching. A simplified conductance network describing the μTEG (KTEG) in parallel with KLK accounting for parasitic thermal leakages and in series with KS representing the conductance to ambient (to

To explore which is the KTEG value that maximizes Pmax, as was done in the

*Equivalent circuit of a μTEG, formed by a voltage source (VOC) and its internal resistance (RTEG), connected in*

both heat source and heat sink) is shown in **Figure 4**.

electrical case, Eq. (2) can be rewritten as:

internal resistance, increasing it, in order to match the load resistance [22]. According to **Figure 3**, this is in fact an error. It is always a better approach to minimize the internal resistance in order to increase the power output even further. Once the internal resistance is the minimum possible, then the load matching condition can be applied to maximize the power output. Actually, many integrated circuits exist which efficiently implement maximum power point tracking (MPPT) algorithms to extract the maximum power from a power source by modifying its

<sup>¼</sup> *<sup>V</sup>*<sup>2</sup> *oc* 4*RTEG*

*RTEG* þ *RL* <sup>2</sup>

� *RL* (1)

(2)

μTEG, formed by a voltage source (VOC) and its internal electrical resistance (RTEG), connected to a load resistance (RL), it is straightforward to evaluate the

2

*PL*, *max* <sup>¼</sup> *<sup>V</sup>*<sup>2</sup>

total dissipated power at the load as:

write the maximum power as:

tance when designing a μTEG.

load resistance.

**Figure 2.**

**354**

*series with a load resistance (RL).*

*PL* ¼ *VL* � *IL* ¼ *I*

*Heat Transfer - Design, Experimentation and Applications*

**Figure 3.** *Power output of a μTEG versus load resistance for different RTEG values.*

$$P\_{L,\max} = \frac{V\_{oc}^2}{4R\_{TEG}} = \frac{\left(\mathbb{S} \cdot \Delta T\right)^2}{4R\_{TEG}}\tag{3}$$

Where *S* is the Seebeck coefficient and ΔT is the temperature difference across the μTEG, or Thot-Tcold from **Figure 4**. Therefore:

$$
\Delta T = \Delta T\_A \frac{K\_S}{(K\_{TEG} + K\_{LK} + K\_S)} \tag{4}
$$

Where ΔTA is the total available temperature difference, Tamb-Thot. KTEG is the internal thermal conductance of the μTEG and KS represents the thermal conductance to the ambient.

When decreasing RTEG, as deemed appropriated in the previous paragraphs, it is important to keep in mind that KTEG is bound to increase, as they are inversely proportional. This is because of the implicit assumption that changing KTEG implies a geometry modification, not a material property change and the geometry change affects both electrical resistance and thermal conductance of the μTEG. Ignoring any leakage contribution (KLK = 0 W/K) in Eq. (4), the power output (solid) and ΔT

(dotted) versus KTEG can be seen in **Figure 5**. Three different KS cases have been considered to highlight the fact that, the larger KS, the larger the power output, even for a constant KTEG. It can be seen that when KTEG = KS, the maximum power condition when KLK = 0, then the temperature drop across the μTEG is 50% of the available temperature difference.

Similar to the electrical case, many papers discussing thermal matching focus on reaching a temperature drop in the μTEG equal to the temperature drop across KS [5, 24, 25]. When this KS represents a heat exchanger, some authors suggest a low KS heat exchanger to match KTEG and therefore maximize the power output according. While this approach assures operation at the mathematical local maximum for a given KS, it is a bad practice because it ignores the absolute maximum, which takes place at larger KS values for a given KTEG.

Looking at **Figure 5**, if KTEG = 1 W/K, this reasoning would imply that KS = 1 W/K would be necessary, and 50% of the total available temperature difference would drop across the μTEG. However, with a better heat exchanger, KS = 10 W/K or even KS = 100 W/K, then ΔT will asymptotically approach ΔTA, and the power output will asymptotically reach:

$$P\_{L,max} = \frac{\left(\mathbb{S} \cdot \Delta T\_A\right)^2}{4R\_{TEG}}\tag{5}$$

**3. Decreasing the platform thermal resistance**

*DOI: http://dx.doi.org/10.5772/intechopen.96246*

*Managing Heat Transfer Issues in Thermoelectric Microgenerators*

shown in section 4.

are available at [26].

steps).

**357**

trical and thermal resistances.

**3.1 Forced convection experiments**

forced to move and then renew by an external force.

As mentioned before, the performance of μTEG devices depends on the temperature difference 'seen' by the thermocouples. Therefore, minimizing thermal resistances in series with those elements would improve the performance of the device. In this section, such improvement is demonstrated by decreasing the thermal resistance between the suspended platform and the ambient, usually the cold part, by favoring the heat flow locally. Two methods have been used to increase such heat exchange: (i) by forcing heat convection onto the platform and (ii) by contacting it with a cold mass. The promising results obtained from the experiments described in the next two subsections call for optimizing this effect through the development of a procedure to integrate a heat exchanging structure, which will be

As the working scenario for the μTEG devices is dominated by a temperature difference between the hot and the cold parts, heat convection could play also an important role on how these temperatures are established. Convection is a mechanism of heat flux originated from the movement of the surrounding fluid, which will be typically air for the usual applications of the presented devices. Depending on how this movement is induced, convection can be classified as natural or forced. Natural convection is based on the warming up of the air that is close to a heat source that, due to the lowering of its density, tends to move upwards, giving its place to colder air and so promoting the heat exchange. In forced convection, air is

In order to demonstrate the improvement in the performance of the device, three different sets of experimental measurements have been performed on a device at three different convection conditions. The first one corresponds to natural convection, which occurs when the device is operated by letting it rest on top of a hot surface exposed to ambient at room conditions. The second and third sets of measurements correspond to forced convection regimes. In the second case, this is accomplished by the use of a standard CPU fan (see **Figure 6**) placed over the device, while in the third, an air jet, obtained through a syringe connected to the compressed air line in the laboratory, is directed towards the device. More details

Such experimental measurements have been performed on two different devices, featuring 30 and 60 μm long silicon NWs (by filling 3 and 6 trenches as described in section 2.1). Consequently, each one of the devices has different elec-

The obtained experimental results are shown in **Figure 7**. The devices have been measured at different temperatures of the hot plate (from 50 to 200 °C in 25 °C

The measurement results show a very clear improvement in the performance as

a result of forced convection. The maximum output power obtained when the device is mounted under the fan is multiplied by 3 when compared with the natural convection regime, while when under the more directed and higher flow air jet, the performance increases nearly three orders of magnitude: from a few nW to almost 0.7 μW. Moreover, the more performant air convection is, the less relevant become the thermal properties of the thermoelectric material. In natural and air forced convection cases, the larger output power corresponds to the longest nanowires, whereas in the air jet forced convection the opposite is true. This happens because the longer nanowires also have a larger electrical resistance, and its larger thermal

In conclusion, both load matching and thermal matching are conditions that are mathematically true, but from a practical point of view, care must be taken when designing a μTEG to maximize its power output. First of all, its electrical internal resistance (RTEG) must be minimized, and after that, power output can be maximized by connecting a load which matches that of the μTEG, or simply an IC implementing an MPPT algorithm. On the thermal side, as RTEG is minimized, the thermal conductance (KTEG) is consequently maximized. Then, as the μTEG is already optimized, and it is not possible to further increase KTEG, the only option is to act on the external components, which in this case is the heat exchanger, and to choose one with an as large as possible KS, so that almost all of the available ΔT will be internally transferred to the μTEG.

#### **Figure 5.**

*Pmax (left, blue curves) and ΔT/ΔTA (right, red curves) versus KTEG for different KS values. For KTEG = 1, thermal matching conditions would call for KS = 1, but larger Pmax values are possible for larger values of KS.*
