Meet the editors

Isiaka A. Alimi received his Ph.D. in Telecommunications Engineering from the University of Aveiro, Portugal. He was with the Federal Radio Corporation of Nigeria as a senior engineer (RF transmission and management) and the Department of Electrical and Electronics Engineering, Federal University of Technology, Akure, Nigeria, as a lecturer. He is currently a researcher at the Instituto de Telecomunicações, Aveiro, Portugal, where he

has been participating in various R&D activities. He has authored/co-authored more than forty technical papers, nine book chapters, and has co-edited one book. His research interests include optical communications, microwave photonics, network security, fixed-mobile broadband (wired and wireless technologies) convergence, and their applications for effective resources management in access networks. He is a member of the Institute of Electrical and Electronics Engineers (IEEE).

Oluyomi Aboderin obtained a Ph.D. in Telecommunications Engineering from the University of Porto, Portugal. He also obtained a master's degree in Personal Mobile and Satellite Communications from the University of Bradford, United Kingdom, and a bachelor's degree from the Ladoke Akintola University of Technology, Nigeria. He joined the National Space Research and Development Agency in 2005 and is currently an assistant direc-

tor with the agency, in the frequency coordination and management team. He was a researcher with Instituto de Telecommunicações, Aveiro, Portugal, and has been participating in various research and development activities. He has published more than ten technical papers, including a patent. His research interests include satellite channel modeling, frequency management, antenna design, underwater communications, and microwave photonics.

Nelson Muga graduated in Physics from the University of Porto, Portugal, in 2002. He received a master's degree in Applied Physics in 2006, and a Ph.D. in Physical Engineering in 2011, both from the University of Aveiro, Portugal. He has been a lecturer in the Physics Department, the University of Aveiro since 2016, where he teaches courses related to optics, optoelectronics, and photonics. Currently, he is an auxiliary researcher at the Insti-

tuto de Telecomunicações, Aveiro, where, over the years, he has participated as a researcher in more than twenty-five R&D projects, developing expertise in the field of high-speed optical communications and quantum-secure optical communication systems and technologies. He has published more than forty papers in international journals and more than sixty international conference proceedings. He is a senior member of the Optical Society.

Antonio Teixeira obtained a Ph.D., partly developed at the University of Rochester, USA, from the University of Aveiro, Portugal, in 1999. He holds an Executive Certificate in Management and Leadership from the MIT Sloan School of Management, Massachusetts, USA, and a post-graduate degree in Quality Management in Higher Education. He joined the University of Aveiro in 1999 and is presently a full professor and a senior researchContents

**Section 1**

**Section 2**

**Section 3**

for Access Networks

**Preface XI**

Process and Component Optimization **1**

**Chapter 1 3**

**Chapter 2 25**

Network Architecture and Design **37**

**Chapter 3 39**

Microstructure Fabrication and Routing Optimization **65**

**Chapter 4 67**

**Chapter 5 85**

Direct and External Hybrid Modulation Approaches

MAS: Maximum Energy-Aware Sense Amplifier Link

*by Isiaka A. Alimi, Romil K. Patel, Oluyomi Aboderin, Abdelgader M. Abdalla, Ramoni A. Gbadamosi,* 

*Nelson J. Muga, Armando N. Pinto and António L. Teixeira*

A Novel Approach for the Design of Fault-Tolerant Routing Algorithms in NoCs: Passage of Faulty Nodes, Not Always Detour

Digital Control of Active Network Microstructures on Silicon Wafers

Network-on-Chip Topologies: Potentials, Technical Challenges,

*by Erulappan Sakthivel and Rengaraj Madavan*

Recent Advances and Research Direction

*by Masaru Fukushi and Yota Kurokawa*

*by Zhongjing Ren, Jianping Yuan and Peng Yan*

for Asynchronous Network on Chip

*by Adebayo E. Abejide, Madhava R. Kota, Sushma Pandey, Oluyomi Aboderin, Cátia Pinho, Mário Lima and António Teixeira*

er in the Instituto de Telecomunicações. Since 2014, he has been the dean of the Doctoral School, University of Aveiro. Dr. Teixeira has worked at several industrial organizations, including Nokia Siemens Networks, Coriant, and PICadvanced, a startup in photonics that he cofounded that employs more than forty highly skilled persons. He holds eleven patents and has published more than 400 papers. He has supervised more than seventy MSc and fifteen Ph.D. students and has participated in more than thirty-five national and international projects.

## Contents


Preface

On-chip communication has been experiencing unprecedented pressure due to the huge amount of intellectual property (IP) cores that can now be integrated on a single chip. For traditional bus-based interconnections, the integration results in scalability and contention issues for on-chip communication. Based on this, they are limited and unable to effectively support the required inter-component communication in the System-on-Chip (SoC). Consequently, the major challenges in many core-based SoCs are related to scalability, flexibility, and a high-performance

Network-on-Chip (NoC) has emerged as an efficient solution for offering the required architectural flexibility and parallelism to support the associated massive cores and IPs. In an NoC system, communication between the cores is a router-based packet-switched transmission. Based on this, for an optimum trade-off between flexibility and energy efficiency, there has been an increase in the implementation of NoC architectures for on-chip communications in embedded multicore processors such as Multiprocessor SoCs (MPSoCs), Chip Multiprocessors (CMPs), and Graphics Processing Units (GPUs). In addition, multicore processing is attractive for power reduction in general-purpose

This book covers the fundamental concepts and the state of the art of NoC architecture. This comprises the exploration of process and component optimization. It also focuses on the cost-effective and appropriate combination of components and processes. In this context, hybrid modulation can be employed for Photonic Integrated Circuits (PICs) to ensure high-performance communication. A traffic-aware sense amplifier can also be employed in an NoC system to alleviate energy consumption. Furthermore, the book focuses on various network architecture and designs for NoC systems. In this regard, recent advances in designfriendly, scalable, flexible, and high-performance interconnection architectures are presented along with the associated technical challenges and research direction for design optimization. Moreover, microstructure fabrication and routing optimization are also covered in this book, as the employed routing algorithm can significantly influence the overall network performance metrics regarding latency

In general, this book not only presents underlying concepts, features, and related evolutions but also clarifies the fundamental technical principles of on-chip communications with good insights into future NoC systems. The information presented is easy to follow, concise, and comprehensible. It comprises both theoretical and practical areas of system implementation. This makes it suitable for students, researchers, and professional engineers. It is also a good reference for all interested readers who wish to keep abreast of the current trends in on-chip

communication backbone.

computing and embedded systems.

communications, especially NoC systems.

and throughput.
