Microstructure Fabrication and Routing Optimization

## **Chapter 4**

## A Novel Approach for the Design of Fault-Tolerant Routing Algorithms in NoCs: Passage of Faulty Nodes, Not Always Detour

*Masaru Fukushi and Yota Kurokawa*

## **Abstract**

Due to the faults in system fabrication and run time, designing an efficient fault-tolerant routing algorithm with the property of deadlock-freeness is crucial for realizing dependable Network-on-Chip (NoC) systems with high communication performance. In this chapter, we introduce a novel approach for the design of fault-tolerant routing algorithms in NoCs. The common idea of the fault-tolerant routing has been undoubtedly to detour faulty nodes, while our approach allows passing through faulty nodes with the slight modification of NoC architecture. As a design example, we present an XY-based routing algorithm with the passage function. To investigate the effect of the approach, we compare the communication performance (i.e. average latency) of the XY-based algorithm with well-known region-based algorithms under the condition of with and without virtual channels. Finally, we provide possible directions of future research on the fault-tolerant routing with the passage function.

**Keywords:** network-on-chip (NoC), fault-tolerant routing, two-dimensional mesh, passage, dependability

## **1. Introduction**

Demand for computation power will never stop, and it is ever increasing year by year in a variety of scientific research fields. As can be seen in the modern multiprocessor system-on-chips and many core systems [1–3], this makes computing hardware devices equip with hundreds or thousands of processor cores for providing high computation power by parallel processing on a chip. For the implementation of such highly-integrated parallel systems, Network-on-Chip (NoC) has emerged as a promising paradigm. In NoCs, each node (i.e. a processor core with a router) is connected by an on-chip network and communication among them are done by transferring packets on the network. Using global interconnection structure reduces the difficulty of wiring design and latency of signal transmission and offers high scalability, in comparison with point-to-point signal wires or shared busses [4].

One of the most important and fundamental issues that must be addressed for NoCs is fault-tolerant routing. Definitely, routing of packets plays a key role in

parallel systems because it has significant impact on the overall system performance. Meanwhile, the occurrence of faults during system fabrication and run time is inevitable, and it is almost impossible to completely remove their adverse effects from the systems even if some redundancy is incorporated. A single faulty node disrupts packet routing between many pairs of nodes, resulting in the failure of the entire system. Besides, a deadlock (i.e. circular waiting of packets) will occur if an adopted routing algorithm is imperfect. Once the deadlock occurs, packets can never proceed to the destinations, and thus resulting in the malfunction of the entire system. Therefore, designing an efficient fault-tolerant routing algorithm with the property of deadlock-freeness is crucial for realizing dependable NoC systems with high communication performance.

So far, extensive research has been devoted to fault-tolerant routing not only for NoCs but for traditional parallel computers. Although there exist several basic approaches, as we reviewed in Section 2, the common idea of the fault-tolerant routing remains unchanged from the earliest, and it has been undoubtedly to detour faulty nodes. This is quite natural because the purpose of the fault-tolerant routing is to route packets from source to destination nodes without entering faulty parts. Meanwhile, it is also obvious that detouring faulty nodes increases the communication latency as the packet is misrouted apart from the minimal path to the destination. One may consider that the increase in the communication latency is very little. This is true if packets are routed without interfered by other packets. However, it can be substantial increase under the situation where a number of packets are routed simultaneously and thus frequently blocked by others.

In this chapter, we introduce a novel approach for the design of fault-tolerant routing algorithms. In contrast to the common idea of detouring faulty nodes, our approach allows passing through them with the slight modification of NoC architecture. We provide a general methodology for designing a fault-tolerant routing algorithm with the passage of faulty nodes. As a design example, we describe an XY-based routing algorithm with the passage function. By computer simulations, we reveal the communication performance of the algorithm under the condition of with and without Virtual Channels (VCs), in comparison with well-known region-based routing algorithms.

The rest of this chapter is organized as follows: Section 2 presents the architecture of NoC, the basis of packet routing, and the related works of fault-tolerant routing algorithms. Section 3 presents the basic idea of the proposed approach and XY-based fault-tolerant routing algorithm, inclusive of the proof of the deadlockfreeness. Section 4 presents the results of the performance evaluation. Finally, Section 5 concludes the chapter with some possible direction of future research.

#### **2. NoC architecture and fault-tolerant routing**

#### **2.1 2D mesh NoC**

Target NoC topology in this chapter is a popular 2D mesh which has nodes of *m* rows and *n* columns. **Figure 1** shows the general architecture of the 2D mesh NoC. Each node is composed of a processor core and a router. The processor core runs assigned computation tasks, which can be either independent one or a part of parallel programs, while the router forwards packets to one of the neighbor routers or its local processor core to support the communication among cores. Each node has a unique address ð Þ *i*, *j* , where *i* ∈*X* ¼ f g 1, 2, ⋯, *m* and *j*∈*Y* ¼ f g 1, 2, ⋯, *n* . In the 2D mesh NoC, a node ð Þ *i*, *j* is connected to at most four neighbor nodes, ð Þ *i* � 1, *j* and ð Þ *i*, *j* � 1 , via two unidirectional links, if *i* � 1∈*X* and *j* � 1∈*Y*. For the ease of

*A Novel Approach for the Design of Fault-Tolerant Routing Algorithms in NoCs: Passage… DOI: http://dx.doi.org/10.5772/intechopen.94773*

**Figure 1.** *Architecture of 2D mesh NoC.*

explanation, positive/negative directions of x (row) and y (column) axes are called east/west and north/south, respectively.

**Figure 2** shows the block diagram of the router. In the typical wormhole routing adopted in NoCs, a packet is divided into a sequence of fixed-size units of data, called flits, and transferred by routers one after another. Each router consists of five input/output units, five routing circuits, a VCs allocator, a crossbar switch, and a switch allocator. When a head flit (i.e. a flit having routing information) is transferred to a router and stored into a buffer in the input unit, the following processes are applied.


**Figure 2.** *Architecture of router.*


The incoming head flit moves to the next router at the fifth cycle if there are no contentions, and the subsequent flits follow it in a pipeline fashion. This is a standard five-cycle router [5]. If no VC is used in an adopted routing algorithm, the router is reduced to a four-cycle router, as the second process (i.e. VC allocation) is omitted.

#### **2.2 Deadlock**

In routing packets in accordance with a routing algorithm, the algorithm must care about the occurrence of deadlocks. Deadlock is a situation where packets wait on one another to release the buffers. **Figure 3** shows an example of a deadlock. In this example, a packet A is routed to the node 2, 1 ð Þ via 1, 1 ð Þ, which is blocked by a packet B at 1, 1 ð Þ. The packet B is also routed to 2, 2 ð Þ via 2, 1 ð Þ, which is blocked by a packet C. The packets C and D are also routed similarly, but blocked by the packets D and A, respectively, resulting in circular waiting of packets. Once a deadlock occurs, packets involved in the circular waiting cannot proceed toward the destinations forever. Therefore, deadlock-freeness must be guaranteed in the routing algorithm.

There have been two approaches to preventing deadlocks; approaches with and without VCs. In the approach with VCs, the original network is multiplexed into several virtual networks by VCs. For example, in **Figure 3**, if packets A and C are supposed to be routed on a virtual network with a VC and packets B and D are on a different virtual network with other VC, then the circular waiting is decomposed and packets get to proceed to the destinations. In the approach without VCs, a routing algorithm is carefully designed so that deadlocks never occur in the original

**Figure 3.** *Example of a deadlock.*

#### *A Novel Approach for the Design of Fault-Tolerant Routing Algorithms in NoCs: Passage… DOI: http://dx.doi.org/10.5772/intechopen.94773*

physical network. For example, in **Figure 3**, if packets A and C are routed via 2, 2 ð Þ and 1, 1 ð Þ, respectively, i.e., forced to move in x-direction first, then no deadlocks occur. This approach has an area advantage over the former approach because the implementation of VCs involves the replication of buffers and control circuits in all input/output units in all routers.

#### **2.3 Related works**

Fault-tolerant routing has been the subject of extensive research not only for NoCs but for traditional parallel computers over the past few decades. Most of the existing fault-tolerant routing algorithms for 2D mesh networks fall into the following three categories: (1) those employ a routing table, (2) those relax the constraints of guaranteed delivery or deadlock-freeness, and (3) those define some form of fault information on routers and detour paths.

In the first category, a routing table is employed in each router to route packets to the destinations. Routing tables contain routing information such as next hops for destinations, status of the network, and/or fault information. Hsin et al. [6] proposed an algorithm which employs ant colony optimization for traffic balancing. Liu et al. [7] proposed an algorithm which introduces coarse and fine-grained lookahead schemes to obtain the information of other routers within the range of four hops. This algorithm requires two VCs for each input/output port to route packets. Zhao et al. [8] proposed an algorithm to provide minimal paths using the information of whole network. In general, those algorithms offer flexible route selection; however, they require a large amount of circuits to implement a routing table and complex calculation mechanism to create/update the table in all routers.

In the second category, constraints of guaranteed delivery or deadlock-freeness is relaxed to ease the design of routing algorithms. Janfaza et al. [9] proposed an adaptive routing algorithm which employs timeout and packet reinjection. Information of intermediate nodes is recorded in each packet and two VCs are used to route packets. Sinha et al. [10] proposed an algorithm based on the common XY and YX routing. This algorithm allows U-turn using several VCs. Wang et al. [11] proposed an algorithm which relaxes transmission accuracy for the applications that allow lossy communication. This algorithm discards conflicting approximate flits without retransmission and recovers them after packet transmission. Those algorithms are imperfect in that 100% packet reachability or deadlock-freeness are not guaranteed by the routing algorithms. Retransmission of packets generally results in a high communication latency.

In the third category, some form of fault information is defined for routers to detour faulty parts. Usually, clusters of faulty nodes, called fault blocks, are defined in the networks with the detour paths. Chen et al. [12], Holsmark et al. [13], Fu et al. [14], and Fukushima et al. [15] proposed routing algorithms which generate rectangular fault blocks and detour them without using VCs. Wu [16] and Chalasani et al. [17] proposed routing algorithms which can deal with convex and nonconvex fault blocks, respectively. In [17], four VCs are used to choose shorter detour paths. Those algorithms called region-based algorithms provide simple but strict routing rules to guarantee the deadlock-freeness and 100% packet reachability, and thus, they can be implemented as a small circuit in the routing circuit of each router. They are practical and suitable for NoCs. However, one drawback is that fault blocks may include several non-faulty nodes, which are to be deactivated (i.e. unused nodes); therefore, the number of unused nodes and the length of detour paths are prone to increase if there exist a number of faulty nodes in the network.

Although extensive research has been devoted to designing fault-tolerant routing algorithms inclusive of the above ones, the common idea remains

unchanged from the earliest, and it has been undoubtedly to detour faulty nodes. If a packet must detour a faulty node ð Þ *i*, *j* , the hop count between ð Þ *i* � 1, *j* and ð Þ *i* þ 1, *j* is increased by two, which increases the communication latency by at least ten cycles in an NoC with five-cycle routers. This can be substantial increase in the situation where the network gets congested (i.e. by packet blocking) or includes a number of faulty nodes (i.e. by detouring). This is a serious problem for a large-scale parallel system on a single VLSI chip.

## **3. Proposed method**

#### **3.1 Basic approach and NoC architecture**

Motivated by the problem presented in the previous section, we introduce a novel approach based on the opposite idea of the common approach; our approach allows packets to pass through the faulty nodes with slight modification of NoC architecture (originally proposed in [18]). Basic idea behind this approach is to reduce communication latency by saving detouring as much as possible.

**Figure 4** shows the modified NoC architecture for supporting the proposed approach. Four electrical switches, bypass links, buffers to store one flit are added around each router. Each switch has two states, either normal or passage, as shown in this figure. In the state of passage, packets from the neighbor node are input to the bypass link not to the node. The switch states can be determined easily, once the node is tested and judged as faulty or not. In other words, they are determined so that the node becomes passage state if it is faulty or remains normal state otherwise. It is worth to note that buffers can be removed if packets are transmitted between routers in an asynchronous way.

#### **3.2 Design methodology for fault-tolerant routing algorithms**

Here, we provide a design methodology for fault-tolerant routing algorithms based on the passage of faulty nodes.

First, we clarify the fault model. A common assumption is made for faults [6, 12–16, 18, 19]; that is, permanent faults are considered to be associated only with nodes. In practice, the probabilities of links, switches, and buffers being faulty are not zero, though they will be substantially small because of the simplicity of their

**Figure 4.** *Modified NoC architecture.*

#### *A Novel Approach for the Design of Fault-Tolerant Routing Algorithms in NoCs: Passage… DOI: http://dx.doi.org/10.5772/intechopen.94773*

circuits [19]. For the faults on those circuits, one can employ some popular redundancy technique such as duplication and triplication if necessary.

Below is the general methodology for designing fault-tolerant routing algorithms with the passage function.

**Step 1** Choose a base routing algorithm from the existing algorithms or design a new one. This algorithm is not necessary to be fault-tolerant, but should be deadlock-free.

**Step 2** Decide which faulty nodes can be passed through and define routing rules for the remaining faulty nodes to be detoured. The resultant routing algorithm, denoted by *R*, is a candidate for the final algorithm.

**Step 3** Verify if the candidate routing algorithm *R* is deadlock-free or not. If not, return to Step 2 to modify *R*.

**Step 4** Repeat Steps 2 and 3 until a fault-tolerant and deadlock-free routing algorithm *R* is obtained.

#### **3.3 Routing algorithm based on XY routing**

As a design example, we introduce a new fault-tolerant routing algorithm based on the popular dimension order routing (i.e. XY routing for 2D meshes) [18]. In the following, we explain the details of each step in the design methodology.

In Step 1, we choose XY routing as a base routing algorithm. In XY routing, packets first proceed along x-direction until they reach the nodes having the same x-coordinates as the destinations, then proceed to the destinations along y-direction without changing the x-coordinates.

In Step 2, we must consider the case where passage must be restricted. For example, suppose that a packet moves from node ð Þ *i* � 1, *j* to ð Þ *i* þ 1, *j* passing through a faulty node ð Þ *i*, *j* . If the destination node is *i*, *j* <sup>0</sup> ð Þ where *j* <sup>0</sup> 6¼ *j*, the packet keeps moving between ð Þ *i* � 1, *j* and ð Þ *i* þ 1, *j* because the x-coordinate of the current node will never be the same as that of the destination node. The same kind of thing never happens in the y-direction. Therefore, we allow packets passing through faulty nodes only in the y-direction and let them detour faulty nodes through the south side in the x-directional movement. (This restriction is relaxed a bit in the final routing algorithm).

Then, we need to consider the case where a faulty node is on the south boundary of the network. In this case, packets cannot detour it through the south side, as they face the south boundary. To cope with this, we give the following definitions.

**Definition 1** A faulty node ð Þ *i*, *j* which is on the south boundary of a mesh network is defined as a South Faulty (SF) node, where *j* ¼ 0*.*

**Definition 2** A faulty node ð Þ *i*, *j* which exists in the eight neighbor of any SF node *i* 0 , *j* <sup>0</sup> ð Þ is also defined as an SF node, where *i* <sup>0</sup> � 1≤*i*≤ *i* <sup>0</sup> ð Þ þ 1 and *i* ∈*X*, and *j* <sup>0</sup> � 1≤*j*≤ *j* <sup>0</sup> ð Þ þ 1 and *j*∈*Y*.

The process in Definition 2 is repeated until no SF nodes are generated. For SF nodes, we give a new routing rule such that packets must detour them through the north side.

In Step 3, we check the deadlock-freeness of the resultant routing algorithm *R* where packets detour faulty nodes/SF nodes through south/north side in the x-directional movement of XY routing and always pass through faulty nodes in the ydirectional movement. Unfortunately, it is not hard to find the case where a deadlock occurs. **Figure 5** illustrates the example of a possible deadlock. Packets generated at nodes S1/S2 detour faulty and SF nodes in accordance with the routing algorithm *R*, but finally they are blocked by each other, resulting in circular waiting. Note that, generally, the deadlock in **Figure 5** can be occurred by more than two packets.

**Figure 6.** *SF area for xy-based routing algorithm.*

To cope with the deadlock, we give the following definitions.

**Definition 3** Let *i* 0 , *j* <sup>0</sup> ð Þ be the coordinates of the north most SF node generated by repeating Definition 2. SF area is defined as the area consisting of all nodes ð Þ *i*, *j* such that *j*≤ *j* <sup>0</sup> for any *i*∈*X*. All faulty nodes in the SF area are changed to SF nodes.

For the newly generated SF nodes in Definition 3, the processes in Definitions 2 and 3 are repeated until no SF nodes are generated.

**Figure 6** illustrates examples of the SF area. In the case of **Figure 6** (a), faulty node (2, 0) is changed to an SF node by Definition 1 and subsequently (3, 1) is changed to an SF node by Definition 2. Then, faulty node (0, 1) on the west boundary is included in the SF area and thus changed to an SF node by Definition 3. Finally, faulty node (0, 2) is changed to an SF node by Definition 2. According to the above processes, the SF area is configured as shown in the figure. In the case of **Figure 6** (b), faulty node (4, 1) is not included in the SF area; hence, faulty nodes (0, 1) and (0, 2) are not changed to SF nodes.

By the above definitions, the deadlock in **Figure 5** can be solved. By Definition 3, two faulty nodes in **Figure 5** are changed to SF nodes and the SF area is defined as shown in **Figure 7**. Then, two packets detour the SF nodes, not faulty nodes, through the north side and get to proceed to the destinations as shown in the figure.

**Figure 8** describes the finally obtained proposed routing algorithm. In this figure, C and D represent a current and a destination node, respectively. The

*A Novel Approach for the Design of Fault-Tolerant Routing Algorithms in NoCs: Passage… DOI: http://dx.doi.org/10.5772/intechopen.94773*

**Figure 7.** *Routing example without deadlocks.*

proposed routing algorithm allows packets to pass through faulty and SF nodes in the movement of x-directions only if C and D are on the same row (i.e. lines 8 and 18 in **Figure 8**), while it always allows passage in the movement of y-directions.

Next, we prove the deadlock-freeness of the proposed algorithm described in **Figure 8**. First, we define turns of packets.

**Definition 4** ES turn is a turn in which an incoming packet from the East neighbor is sent to the South neighbor at a router. Other seven turns are also defined similarly as shown in **Figure 9***.*

**Theorem 1** The routing algorithm in **Figure 8** is deadlock-free.

**Proof.** We prove that circular waiting of packets never occurs in both clockwise and counter-clockwise directions.

For the clockwise direction, we show that an SW turn is never aligned with an NE turn. The SW turn occurs in a non-SF area; however, the NE turn never occurs

**Figure 8.** *A pseudo-code of the proposed routing algorithm.*

#### *Network-on-Chip - Architecture, Optimization, and Design Explorations*

**Figure 9.** *Possible eight turns of packets.*

in the area because it only occurs in an SF area. Conversely, the NE turn occurs in an SF area; however, the SW turn only occurs in a non-SF area. From the above, circular waiting never occurs in the clockwise direction.

For the counter-clockwise direction, we omit the proof because it is symmetrical to the proof for the clockwise direction.

Thus, the proposed routing algorithm is proved to be deadlock-free. □

#### **4. Performance evaluation**

#### **4.1 Evaluation condition**

To investigate the effect of the proposed approach, we have conducted computer simulations with a cycle-accurate custom simulator developed in C. This simulator accurately simulates the behavior of flits in all routers in a 2D mesh NoC. As explained in Section 2, if there are no contentions, each flit takes five (or four) cycles to move to the next node when VCs are used (or not used) in the adopted routing algorithm. Note that, as flits are transmitted in a pipeline fashion, a subsequent flit moves to the next node one cycle after the movement of the precedent flit if buffer space is available in the input unit of the router. It also takes one cycle to pass through a faulty node, as a buffer is placed on the bypass link.

Following three methods are evaluated in the simulations with the parameters listed in **Table 1**.

• Fukushima's method [15]: packets detour *rectangular* fault blocks with no additional VCs (denoted by *Mr*).


**Table 1.** *Simulation parameters.* *A Novel Approach for the Design of Fault-Tolerant Routing Algorithms in NoCs: Passage… DOI: http://dx.doi.org/10.5772/intechopen.94773*


The number of VCs required for each algorithm is different, and VCs can also be employed in the algorithms which require no VCs for the purpose of congestion avoidance. We use the notation of *M*-*n* to indicate the number of VCs (i.e. buffers), where *M* is either *Mr*, *Mnc* or *Mp* and *n* represents the number of VCs. For example, *Mnc*-4 denotes Chalasani's method with four VCs; *Mp*-1 denotes our proposed method with one buffer (i.e. no additional VCs).

In the simulations, faulty nodes are generated randomly according to the fault rate *f*, and packets are also generated randomly at each cycle according to the packet generation rate *p* during the simulation time of 50,000 cycles. Latency is not measured up to 5000 cycles to stabilize the network. The same fault patterns are used for all methods for fair comparison. The above trial is repeated 1000 times and the following metrics are measured.

**Average latency** is defined by the average cycles required for packets from the generation to the arrival.

**Average node utilization rate** is defined as the percentage of available nodes among all non-faulty nodes, i.e., given by f g *mn*ð Þ� 1 � *f u =mn*ð Þ 1 � *f* , where *m* and *n* is the number of rows and columns, respectively, *f* is the fault rate, and *u* is the number of unused nodes.

To make a quantitative evaluation of average latency, we define maximum latency reduction rate of an algorithm *Ma* for an algorithm *Mb* by

$$R(M\_a, M\_b) = \max\_{p} r\_p(M\_a, M\_b),\tag{1}$$

where *rp*ð Þ *Ma*, *Mb* represents latency reduction rate of *Ma* for *Mb* at the packet generation rate *p* and is defined by the following expression.

$$r\_p(M\_a, M\_b) = \frac{L\_b - L\_a}{\max\left(L\_a, L\_b\right)} \times 100,\tag{2}$$

where *La* and *Lb* is the average latency of *Ma* and *Mb* at *p*, respectively, and *max L*ð Þ *<sup>a</sup>*, *Lb* is a function to return the larger of *La* and *Lb*.

#### **4.2 Evaluation results**

#### *4.2.1 Overall trend*

**Figures 10**–**14** show the average latency as a function of packet generation rate *p* for each fault rate *f*. In the figures, x axis represents *p*, and a larger value indicates a higher request load; meanwhile, y axis represents average latency, and a larger value indicates higher delay in delivery of packets. When *p* is relatively low, the average latency of three algorithms is almost the same. On the other hand, when it is high, the difference becomes significant. The average latency of *Mp* and *Mnc* is smaller than that of *Mnc* and *Mr*, respectively, regardless of *f* and the number of VCs. *Mp* outperforms *Mnc* without using VCs, indicating that passage of faulty nodes has a significant impact on reducing average latency. As *f* increases, the

**Figure 10.** *Average latency for f* ¼ 2%*.*

**Figure 11.** *Average latency for f* ¼ 4%*.*

**Figure 12.** *Average latency for f* ¼ 6%*.*

*A Novel Approach for the Design of Fault-Tolerant Routing Algorithms in NoCs: Passage… DOI: http://dx.doi.org/10.5772/intechopen.94773*

**Figure 13.** *Average latency for f* ¼ 8%*.*

**Figure 14.** *Average latency for f* ¼ 10%*.*

average latency of those algorithms is increased due to the increased number of faulty nodes.

**Figure 15** shows the average node utilization rate. *Mr* and *Mnc* generate rectangular and nonconvex fault blocks, and accordingly, about 7% and 3% of non-faulty nodes become unused nodes, respectively. This is a cause of longer detour paths. Meanwhile, *Mp* does not generate any fault blocks and always keeps 100% utilization rate.

For the results shown in **Figures 10**–**14**, we make performance comparison of the routing algorithms in the following three conditions.

#### *4.2.2 Performance comparison of the original routing algorithms*

The average latency of the original routing algorithms is compared numerically (i.e. comparison of *Mr*-1, *Mnc*-4, and *Mp*-1). **Table 2** shows the maximum reduction rate of *Mr*-1 and *Mp*-1 for *Mnc*-4. The value of *p* at which the maximum reduction rate is attained is noted in parenthesis. As we saw in **Figures 10**–**14**, average latency of *Mr* is higher than that of *Mnc*; hence, all rates of *R M*ð *<sup>r</sup>*-1, *Mnc*-4) are negative

**Figure 15.** *Average node utilization rate vs. fault rate.*


#### **Table 2.**

*Maximum latency reduction rate R M*ð Þ *<sup>a</sup>*, *Mb for the original algorithms.*

values for any *f*. From this table, we found that *Mp*-1 reduces the average latency of *Mnc*-4 by about at least 79% without using additional VCs.

#### *4.2.3 Performance comparison of routing algorithms with increased VCs*

Next, the average latency of the three algorithms is compared by increasing the number of VCs twofold, threefold, and fourfold from the original (i.e. comparison of *M*<sup>∗</sup> -*n*, *M*<sup>∗</sup> -2*n*, *M*<sup>∗</sup> -3*n*, and *M*<sup>∗</sup> -4*n*). **Table 3** shows the results. The following can be found in the evaluation results:


#### *4.2.4 Performance comparison of routing algorithms with fixed number of VCs*

Finally, the average latency of the three algorithms is compared under the same number of VCs (i.e. comparison of *Mr*-4, *Mnc*-4, and *Mp*-4). **Table 4** shows the maximum reduction rates of *Mr*-4 and *Mp*-4 for *Mnc*-4. By using four VCs, the


*A Novel Approach for the Design of Fault-Tolerant Routing Algorithms in NoCs: Passage… DOI: http://dx.doi.org/10.5772/intechopen.94773*

#### **Table 3.**

*Maximum latency reduction rate R M*ð Þ *<sup>a</sup>*, *Mb for the algorithms with increased VCs.*


**Table 4.**

*Maximum latency reduction rate R M*ð Þ *<sup>a</sup>*, *Mb for the algorithms with four VCs.*

maximum reduction rates of *Mr*-4 and *Mp*-4 can be improved from the rates shown in **Table 2**, and *Mp*-4 always achieves more than 94% reduction rates for any *f*.

From the above results, we can conclude that, for reducing average latency of packet transmission, the reduction of hop count by the passage of faulty nodes, not always detour, is more effective than the avoidance of congestion using additional VCs.

#### **4.3 Circuit amount**

To evaluate the overhead of additional circuits such as switches, buffers, and links in the proposed approach, we designed two routers for *Mr*-1 and *Mp*-1 with Verilog HDL. In those routers, *Mr* and *Mp* are implemented into the routing circuits and the depth of input/output buffers is eight/one flits, respectively, as in the simulation setting. We used Xilinx Vivado EDA tool for synthesizing the routers for the target FPGA device of Vertex 7 xc7vx485tffg1761–2.

From the EDA tool, the router for *Mr* needs 1865 Look Up Tables (LUTs) in the FPGA device, while that for *Mp* needs 664 LUTs, which indicates about 64% LUT reduction. This is mainly because of the difference in the routing circuit; one routing circuit costs 193 LUTs for *Mr* and 18 LUTs for *Mp*. The small routing circuit is also benefit from the passage function. The additional circuits require only 27 LUTs, which is substantially small compared with the overall router circuit.

#### **5. Conclusion and future work**

We have introduced a novel approach for the design of fault-tolerant routing algorithms in 2D mesh NoCs. In contrast to the common idea of detouring faulty nodes, our approach allows passing through them with the slight modification of NoC architecture. We have provided a general methodology for designing faulttolerant routing algorithms with the passage of faulty nodes, and as a design example, we have described the XY-based routing algorithm, showing how to prevent deadlocks in the routing rules. The XY-based routing algorithm allows passage of faulty nodes in the x-directional movement if the current and destination nodes are on the same row, while always allows in the y-directional movement.

To demonstrate the effect of the XY-based routing algorithm, we measured the average latency of packet transmission by computer simulations and compared with those of the well-known region-based algorithms proposed by Fukushima et al. and Chalasani et al. The results revealed that the XY-based algorithm reduced average latency of Chalasani's algorithm by about 79% without additional VCs and 94% with the same number of VCs. From the evaluation, we have found that passage is highly effective approach to reducing the average latency rather than employing VCs for congestion avoidance. We have also designed router circuit for the XY-based algorithm and showed that the overhead of additional circuit required for the proposed approach is substantially small compared with the overall router circuit.

As the passage of faulty nodes is a simple but effective approach, we have even more room to fully investigate the effect. For example, in this chapter, we selected popular XY routing as a base algorithm, which is a deterministic routing algorithm. Designing a new routing algorithm with the passage function based on some adaptive routing algorithm is a possible future research. As the passage is not limited to 2D mesh NoCs, designing passage-based fault-tolerant routing algorithms for other popular topology such as 2D torus, 3D mesh/torus is also one of the interesting future researches.

## **Acknowledgements**

This work was supported by JSPS KAKENHI Grant Number JP18K11217.

## **Author details**

Masaru Fukushi\*† and Yota Kurokawa† Graduate School of Sciences and Technology for Innovation, Yamaguchi University, Ube, Japan

\*Address all correspondence to: mfukushi@yamaguchi-u.ac.jp

† These authors contributed equally.

© 2020 The Author(s). Licensee IntechOpen. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/ by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

*A Novel Approach for the Design of Fault-Tolerant Routing Algorithms in NoCs: Passage… DOI: http://dx.doi.org/10.5772/intechopen.94773*

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## Digital Control of Active Network Microstructures on Silicon Wafers

*Zhongjing Ren, Jianping Yuan and Peng Yan*

## **Abstract**

This chapter presents a promising digital control of active microstructures developed and tested on silicon chips by current division and thus independent Joule heating powers, especially for planar submillimeter two-dimensional (2-D) grid microstructures built on silicon wafers by surface microfabrication. Current division on such 2-D grid networks with 2 2, 3 3, and n n loops was modeled and analyzed theoretically by employing Kirchhoff's voltage law (KVL) and Kirchhoff's current law (KCL), which demonstrated the feasibility of active control of the networks by Joule heating effect. Furthermore, *in situ* testing of a typical 2-D microstructure with 2 2 loops by different DC sources was carried out, and the thermomechanical deformation due to Joule heating was recorded. As a result, active control of the current division has been proven to be a reliable and efficient approach to achieving the digital actuation of 2-D microstructures on silicon chips. Digital control of such microstructural networks on silicon chips envisions great potential applications in active reconfigurable buses for microrobots and flexible electronics.

**Keywords:** surface microfabrication, current division, joule heating, digital control, grid microstructures

#### **1. Introduction**

Silicon-based microelectromechanical systems (MEMS) devices, including sensors, actuators, and generators, show wide applications in microrobots [1], medical devices [2, 3], and flexible electronics [4]. Such miniaturized systems, on one hand, offer great potentials for improving the abilities of micromanipulation and functioning in some extreme conditions, such as limited working space and large displacements; On the other hand, however, the strong requirement of precise and effective control of these kinds of devices is not easy. Therefore, microstructures allowing for reliable and efficient actuation and large displacement are worth investigating.

Thermal microactuators have been proven to be able to realize large displacements more efficiently, and a variety of materials, for example, ceramics [5–7], polymers [8], composites [1, 9, 10], and metals [11–14], are available for building such active microstructures. Moreover, the geometries of these microstructures heavily depend on the selected materials, among which electrothermal bilayer beams have obvious advantages on large displacements, low costs, and high compatibility with mature microfabrication processes. Many efforts have been paid to develop electrothermal microstructures based on different applications and requirements. A safety and arming device composed of two V-shape electrothermal actuators was built, and the design of a cascaded V-beam amplification and two mechanical sliders enabled large deformation. As a result, a large planar displacement of 231.78 μm was achieved by applying a voltage of 15 V [15]. A typical Ushape electrothermal actuator made of a single material allowing for planar bending due to the thermal mismatch between the cold and hot arms was developed. Since the Joule heating power on the narrower arm was smaller than the wider one, the thermal expansion on the narrower (or hot) arm is larger than that of the wider (or cold) arm [16]. Another representative study is related to high frequency, low power, electrothermal bimorph actuators with shape memory effects, and the significant thermal mismatch and shape memory effect contributed to very large out-of-plane deformation [17].

However, previous research on electrothermal actuators usually focused on development beams with simple geometries, such as bridges, V-shape, U-shape, etc. The current flows through the beams were the same, which limited their ability of reconfiguration. To accomplish diverse reconfiguration of such electrothermal microstructures, active current division across planar (or 2-D) bilayer microstructures offers a promising approach to digital control of microstructures for distributed thermal balance and thus various deformations.

Our group has been endeavoring to design, fabrication, and characterization of 2-D multilayered microstructure consisting of beams for out-of-plane deflection, vertical deployment [18–24], and twisting under electrothermal actuation [9]. These microstructures can be created on whole wafers and tested separately by cutting the silicon wafer into chip-scale pieces [18]. Active parts of such microstructures are released by selective etching on the silicon substrates, while the anchored parts are protected from being etched. Different Joule heating powers and balanced temperatures on the grid networks could be obtained. However, instead of qualitative analysis, it is more important and meaningful to quantify the effect of electrothermal effect of bilayer 2-D microstructures, which will lay a solid foundation for modeling and predicting their potentials for large out-of-plane displacement.

The rest of this chapter is organized as follows. In Section 2, theoretical analysis of current divisions in some typical 2-D grid microstructures is firstly carried out, followed by the quantitative analysis of the equivalent resistance and Joule heating power. After that, fabrication and characterization of electrothermal and thermomechanical performances are presented experimentally in Section 3. The results are then shown and discussed in Section 4. Finally, the chapter is concluded in Section 5.

#### **2. Theoretical analysis of current divisions**

In this section, Kirchhoff's Voltage Law (KVL) and Kirchhoff's Current Law (KCL) are employed appropriately to figure out the feasible current division in several representative 2-D grid structures. Note that the scale of the 2-D structures does not change the relative division ratios between these beams. So, we consider more general structures, instead of only microstructures, in this section. It also hints that such cross-scale research on the current distribution is applicable to multiple surroundings and uses. For the sake of simplicity, all the grid structures presented in this chapter are composed of bilayer beams with the same materials and dimensions. Furthermore, these beams are incorporated into grid networks with different geometries. Two representative 2-D grid structures with the 2 2 loops and 3 3 loops are shown in **Figure 1**, where the candidate input ports are marked as red dots. The 2 2 grid structure consists of 12 beams for the current division, while the *Digital Control of Active Network Microstructures on Silicon Wafers DOI: http://dx.doi.org/10.5772/intechopen.101486*

**Figure 1.** *Schematic views of two planar grid structures for the current division.*

3 � 3 one consists of 24 beams. Besides that, it is worth noting that grid structures with n � n loops can be similarly proven to be made of 2n(n + 1) beams.

Let us start with studying the current division through 2 � 2 grid structures by assuming that a constant voltage *V* is applied to any two outer red nodes, as seen in **Figure 1**. To ensure the stable connection between the voltage source and the red input nodes, another two supporting beams with fixed ends anchored on silicon wafers are designed. Hence, it can be derived simply that there are six independent cases in total for voltage inputs, as illustrated in **Figure 2**. The resistances of the beams in grid structures, as well as those of the two supporting beams, are assumed to be the same *R*. To acquire the current distribution through these beams of all the cases, KCL and KVL are adopted to the nodes and loops, respectively. Taking Case 1 as an example, as presented in **Figure 3**, nine independent KCL equations at the nodes Ni (i = 1, 2, … ,9) and five independent KVL ones at the loops Ci (i = 1,2, … ,5) are established, as shown in Eq. [1].

Specifically, the KCL equations could be written as

$$\begin{cases} I\_1 - I\_2 - I\_4 = \mathbf{0} \\ I\_2 - I\_3 - I\_5 = \mathbf{0} \\ I\_3 - I\_6 = \mathbf{0} \\ I\_4 - I\_7 + I\_8 + I\_{10} = \mathbf{0} \\ I\_5 - I\_8 + I\_9 - I\_{11} = \mathbf{0} \\ I\_6 - I\_9 - I\_{12} = \mathbf{0} \\ -I\_{10} + I\_{13} = \mathbf{0} \\ I\_{11} - I\_{13} + I\_{14} = \mathbf{0} \\ I\_{12} - I\_{14} = \mathbf{0} \end{cases} \tag{1}$$

while the KVL equations are formulated as

$$\begin{cases} V - \left(I\_1 + I\_4 + I\_7\right) \cdot R = \mathbf{0} \\\\ I\_4 \cdot R - \left(I\_2 + I\_5 + I\_8\right) \cdot R = \mathbf{0} \\\\ I\_5 \cdot R - \left(I\_3 + I\_6 + I\_9\right) \cdot R = \mathbf{0} \\\\ I\_8 \cdot R - \left(I\_{10} + I\_{11} + I\_{13}\right) \cdot R = \mathbf{0} \\\\ \left(I\_9 + I\_{11}\right) \cdot R - \left(I\_{12} + I\_{14}\right) \cdot R = \mathbf{0} \end{cases} \tag{2}$$

As a result, the 14 unknowns *Ii* (i = 1, 2, … , 14) can be uniquely solved by the derived 14 independent equations, that is,

#### **Figure 2.**

*Six independent cases of voltage inputs into grid structures with 2 2 loops. The red arrows denote the current directions, while the red numbers represent the current division factors between different beams in each case. Note that factors of beams without current flow are 0.*

**Figure 3.** *KCL and KVL on case 1 of the grid structures with 2 2 loops and two supporting beams.*

*Digital Control of Active Network Microstructures on Silicon Wafers DOI: http://dx.doi.org/10.5772/intechopen.101486*

$$\begin{cases} I\_1 = I\_7 = \frac{24}{65} \cdot \frac{V}{R} \\\\ I\_2 = \frac{7}{65} \cdot \frac{V}{R} \\\\ I\_3 = I\_6 = I\_{10} = I\_{13} = \frac{2}{65} \cdot \frac{V}{R} \\\\ I\_4 = \frac{17}{65} \cdot \frac{V}{R} \\\\ I\_5 = I\_8 = \frac{5}{65} \cdot \frac{V}{R} \\\\ I\_9 = I\_{11} = I\_{12} = I\_{14} = \frac{1}{65} \cdot \frac{V}{R} \end{cases} \tag{3}$$

which demonstrates the determination of current division factors for all the beams in Case 1. Similarly, the current division factors in Cases 2–6 can be obtained uniquely, as seen in **Figure 2**.

Further investigation on the current distribution across planar structures with 3 � 3 loops was taken, and the division factors and directions of the current flows had been proved to be unique. Generally, there are 12 independent cases for voltage inputs, as seen in **Figure 4**. Particularly, current distributions of two representative geometries with 3 � 3 loops, Case 3 and Case 6, are solved and illustrated in **Figure 5**. A very interesting phenomenon observed in Case 3 of the 3 � 3 loops structure is that the current division factors are symmetric about the central axis marked as a green dashed line in **Figure 5**. Further exploration reveals that the

**Figure 4.** *Twelve independent cases of voltage inputs into grid structures with 3* � *3 loops.*

**Figure 5.** *Current distributions of two representative cases of voltage inputs into grid structures with 3 3 loops.*

**Figure 6.** *Current distribution across an n n loops geometry like Case 6 in Figure 5.*

directions of current flows symmetrical about the green line are opposite, and the magnitudes of the currents closer to the input ports tend to be larger. In addition, though the distribution regularity of Case 6 is a little more complicated than that of *Digital Control of Active Network Microstructures on Silicon Wafers DOI: http://dx.doi.org/10.5772/intechopen.101486*

#### **Figure 7.**

the Case 3, a very interesting symmetric current distribution about the diagonal of the geometry is found. Similarly, current flows through more complex geometries with n n loops like Case 6 are shown in **Figures 6** and **7**. It is worth noting that the corresponding current division factors in **Figure 6** are represented by Ei (E2 = 2E1, En = En-1 + En-2 when n ≥ 3 and n is odd, En = (En-1 + En-2)/2 when n ≥ 3 and n is even). Generally, there are (2n 2) different currents through the n n grid network, enabling digital control of diverse and regional Joule heating powers across such a 2-D network.

Based on the current divisions of 2 2 loops structures with diverse voltage inputs' cases presented and discussed in this section, the effect of Joule heating on such conductive grid structures is available to be quantified and evaluated.

Assuming that the resistances of a single beam in the 2 2 loops, as well as each of the supporting beams, are the same, *R*, and the external voltages applied are *V*, The equivalent resistances of each case of the 2 2 grid structures shown in **Figure 2** can be solved using KCL and KVL laws, which was presented in the previous research. The Joule heating power of the grid structures and supporting beams can be then determined and listed in **Table 1**, where *Ri* represents the resistance in case *i*, while the *Pi* represents the heating power when a voltage of *V* applied. It can be seen clearly from **Table 1** that equivalent resistances are approximately three times over the resistance of a single beam, and thus the expected Joule heating power is about one-third of the power when a single beam is applied by a voltage of *V*.

Similarly, the equivalent resistances of the 3 3 loops structure in Case 3 and Case 6 can be derived to be 293/56R and 27/7R, respectively.


**Table 1.**

*Equivalent resistances and joule heating powers of the six cases of 2 2 loops with two supporting beams.*

## **3. Experimental validation of 2-D microstructures**

## **3.1 Fabrication of 2-D grid microstructures**

To demonstrate the effect of electrothermal actuation of the 2-D structures, a series of ultrathin (or 2-D) microstructures consisting of grid beams and supporting beams that are mentioned in Section 2 are designed, fabricated, and tested.

Several previous research by our group can be referred to on a typical design and fabrication processes of such 2-D microstructures with two different materials. Specifically, aluminum and NiTi alloys (which are in the austenite phase in the range of testing temperatures) are selected as the bottom layer and top layer, respectively. What needs to be emphasized here is that although NiTi alloys show great potential for shape memory effects, this effect is not introduced intentionally in this research. It is the effect of digital Joule heating that we want to present in this chapter. Aluminum was chosen due to its significantly larger coefficient of thermal expansion than that of the NiTi alloys in the austenite phase.

As a result, a typical 2-D microstructure with the geometry presented in **Figure 3** was imaged by the SEM after being selectively released from the silicon chip, as seen in **Figure 7**. It is worth noting that these two contact pads attached to the silicon chip were connected to gold wires with a diameter of 20 μm. The gold wire was used for electrical signal transfer from the logic printed circuit board after being fixed on the *in situ* imaging stage in SEM.

## **3.2 Results and discussion of** *in situ* **test of the microstructure**

The experimental setup for *in situ* electrothermal actuation of the microstructure is illustrated in **Figure 8**. The stage of the SEM was tilted from zero degree to 45 degree for easier observation and measurement, and the configuration of the microstructure without heating was reimaged as shown in **Figure 9**. The *in situ* electrothermal testing of such a microstructure on the silicon chip started with the

**Figure 8.** *Experimental setup of microstructures on the silicon chip for testing.*

*Digital Control of Active Network Microstructures on Silicon Wafers DOI: http://dx.doi.org/10.5772/intechopen.101486*

**Figure 9.** *SEM image of the microstructure after being tilted by 45 degrees.*

**Figure 10.** *SEM images of microstructures under different driving voltages in electrothermal testing.*

application of a DC source by the Agilent 4155C Semiconductor Parameter Analyzer. The shapes of the microstructure under constant voltages of 12 mV, 15 mV, 18 mV, and 19 mV were imaged and presented in **Figure 10**, and a supplementary video about this process was recorded simultaneously. It can be seen from **Figure 10**, as well as the video, that the microstructure could be digitally actuated by distributed currents for diverse and regional Joule heating. Therefore, the effect of active control of microstructures using digitally distributed currents is demonstrated. It is important to highlight that although the "digital currents" were inherently ensured, the thermomechanical reconfiguration of corresponding beams does not seem to be that "digital". It could be explained by the effect of scaling which could have a significant influence on the thermal conduction between the beams. The scaling effect is expected to be alleviated gradually with structural scale-up. Generally, such silicon chip-based microfabrication processes show great compatibility, effectivity, and efficiency in the development and validation of 2-D microstructures.

### **4. Conclusions**

In conclusion, effective and efficient development of active control of 2-D microstructures based on silicon chips is presented in this chapter. Representative planar structures composed of grid beams are introduced to quantitatively analyze possible current distribution across the conductive geometry using KCL and KVL. Diverse current divisions of structures with different loops and voltage inputs have been proven to be available for digital control of electrothermal actuators. Besides that, the determination of equivalent resistances and resulting Joule heating powers have contributed to the evaluation of *in situ* experiments on the representative microstructure created on silicon chips by microfabrication. The process and critical steps of thermomechanical deformation of such a microstructure are shown to demonstrate the effect of digital control by Joule heating. The unsignificant digital deformation could be attributed to the scale effect of thermal conduction.

It is worth highlighting that much more various and precise current divisions can be obtained by superposition of different voltage inputs, which can be an attractive topic in the future. Another promising research is to investigate the scale effect on Joule heating in different current distributions.

#### **Acknowledgements**

The authors would like to thank Dr. Chang-Yong Nam, Dr. Camino Fernando, and Dr. Ming Lu from the Center of Functional Nanomaterials, Brookhaven National Laboratory. In addition, I really appreciate the great supports and suggestions from Robert Bauer and Yang Xu from Stevens Institute of Technology. The National Natural Science Foundation of China (No.11572248) and China Scholarship Council has in part supported the research. The research was in part carried out at the Center for Functional Nanomaterials (CFN), Brookhaven National Laboratory (BNL), which is supported by the U.S. Department of Energy, Office of Basic Energy Sciences, under Contract No. DE-SC0012704.

#### **Conflict of interest**

The authors declare no conflict of interest.

*Digital Control of Active Network Microstructures on Silicon Wafers DOI: http://dx.doi.org/10.5772/intechopen.101486*

## **Author details**

Zhongjing Ren1 \*, Jianping Yuan<sup>2</sup> and Peng Yan<sup>1</sup>

1 Key Laboratory of High-Efficiency and Clean Mechanical Manufacture (Ministry of Education), School of Mechanical Engineering, Shandong University, Jinan, Shandong Province, China

2 National Key Laboratory of Space Flight Dynamics, School of Astronautics, Northwestern Polytechnical University, Xi'an, Shaanxi Province, China

\*Address all correspondence to: zren@sdu.edu.cn

© 2021 The Author(s). Licensee IntechOpen. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/ by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

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## *Edited by Isiaka A. Alimi, Oluyomi Aboderin, Nelson J. Muga and António L. Teixeira*

Limitations of bus-based interconnections related to scalability, latency, bandwidth, and power consumption for supporting the related huge number of on-chip resources result in a communication bottleneck. These challenges can be efficiently addressed with the implementation of a network-on-chip (NoC) system. This book gives a detailed analysis of various on-chip communication architectures and covers different areas of NoCs such as potentials, architecture, technical challenges, optimization, design explorations, and research directions. In addition, it discusses current and future trends that could make an impactful and meaningful contribution to the research and design of on-chip communications and NoC systems.

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Network-on-Chip - Architecture, Optimization, and Design Explorations

Network-on-Chip

Architecture, Optimization,

and Design Explorations

*Edited by Isiaka A. Alimi, Oluyomi Aboderin,* 

*Nelson J. Muga and António L. Teixeira*