*Edited by Isiaka A. Alimi, Oluyomi Aboderin, Nelson J. Muga and António L. Teixeira*

Limitations of bus-based interconnections related to scalability, latency, bandwidth, and power consumption for supporting the related huge number of on-chip resources result in a communication bottleneck. These challenges can be efficiently addressed with the implementation of a network-on-chip (NoC) system. This book gives a detailed analysis of various on-chip communication architectures and covers different areas of NoCs such as potentials, architecture, technical challenges, optimization, design explorations, and research directions. In addition, it discusses current and future trends that could make an impactful and meaningful contribution to the research and design of on-chip communications and NoC systems.

ISBN 978-1-83968-148-6

Network-on-Chip - Architecture, Optimization, and Design Explorations

Published in London, UK © 2022 IntechOpen

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