Preface

On-chip communication has been experiencing unprecedented pressure due to the huge amount of intellectual property (IP) cores that can now be integrated on a single chip. For traditional bus-based interconnections, the integration results in scalability and contention issues for on-chip communication. Based on this, they are limited and unable to effectively support the required inter-component communication in the System-on-Chip (SoC). Consequently, the major challenges in many core-based SoCs are related to scalability, flexibility, and a high-performance communication backbone.

Network-on-Chip (NoC) has emerged as an efficient solution for offering the required architectural flexibility and parallelism to support the associated massive cores and IPs. In an NoC system, communication between the cores is a router-based packet-switched transmission. Based on this, for an optimum trade-off between flexibility and energy efficiency, there has been an increase in the implementation of NoC architectures for on-chip communications in embedded multicore processors such as Multiprocessor SoCs (MPSoCs), Chip Multiprocessors (CMPs), and Graphics Processing Units (GPUs). In addition, multicore processing is attractive for power reduction in general-purpose computing and embedded systems.

This book covers the fundamental concepts and the state of the art of NoC architecture. This comprises the exploration of process and component optimization. It also focuses on the cost-effective and appropriate combination of components and processes. In this context, hybrid modulation can be employed for Photonic Integrated Circuits (PICs) to ensure high-performance communication. A traffic-aware sense amplifier can also be employed in an NoC system to alleviate energy consumption. Furthermore, the book focuses on various network architecture and designs for NoC systems. In this regard, recent advances in designfriendly, scalable, flexible, and high-performance interconnection architectures are presented along with the associated technical challenges and research direction for design optimization. Moreover, microstructure fabrication and routing optimization are also covered in this book, as the employed routing algorithm can significantly influence the overall network performance metrics regarding latency and throughput.

In general, this book not only presents underlying concepts, features, and related evolutions but also clarifies the fundamental technical principles of on-chip communications with good insights into future NoC systems. The information presented is easy to follow, concise, and comprehensible. It comprises both theoretical and practical areas of system implementation. This makes it suitable for students, researchers, and professional engineers. It is also a good reference for all interested readers who wish to keep abreast of the current trends in on-chip communications, especially NoC systems.

The editors would like to acknowledge and appreciate all the contributing authors. Their works and innovations in different areas of NoC systems are highly appreciated. The editors would also like to thank IntechOpen for the invitation to participate in this project.

> **Isiaka A. Alimi, Oluyomi Aboderin and Nelson J. Muga** Instituto de Telecomunicações, Aveiro, Portugal

### **António L. Teixeira**

Department of Electronics, Telecommunications and Informatics, University of Aveiro and the Instituto de Telecomunicações, Aveiro, Portugal Section 1
