**2. Basics of QCA**

No voltage or current is used. It is possible to replace the gate of a transistor by a molecular charge center and encode information in its charge state. The electrons residing in the diagonally opposite positions lead to two equivalent energy states representing logic '0' and logic '1' which are respectively called as cell polarizations P = +1.00 and P = −1.00 as shown in **Figure 1b**. The clocking is the key element of QCA circuitry as shown in **Figure 1a**. The two basic logic gates in QCA are inverter and majority voter as depicted in **Figure 1d** and **e**. A cell changes its polarization based on the fixed polarization of the cell placed by its side. This feature of QCA cell is exploited when QCA cells arranged in a series act similar to wire as shown in **Figure 1c**.

### **3. Related works**

#### **3.1 An overview of previous 3-input QCA XOR gates**

Exclusive OR (XOR) is an applicable gate for designing the most of logic circuits. This gate has a wide range of applications, particularly in designing circuits such as full-adders, multipliers, dividers, and compressors. Until now, a number of XOR gates have been reported. Angizi et al. in [16] reported an XOR gate that required 94 cells and occupied 0.073 μm2 area. Moreover, the time delay of this gate is 1.5 clock cycles. One of the simplified structures of the XOR gate has been introduced by Ahmad et al., in [17], which requires 14 cells, occupies 0.022 μm2 area and output appears after 0.5 clock cycle. However, this gate cannot achieve the expected

**Figure 1.**

*(a) Four stages of clock (b) logic "0" and "1" states (c) wires for circuit (d) 3-input MG (e) invert.*

*A Novel Three-Input XOR Gate Based on Quantum Dot-Cellular Automata with Power… DOI: http://dx.doi.org/10.5772/intechopen.95554*

### **Figure 2.**

*The QCA representation of the previous 3-input XOR gate in (a) [20], (b) [19], (c) [17], (d) [18], (e) [16].*

optimization for the larger circuit. Bahar et al. have reported another compact XOR gate, in [18] that used 12 cells and occupied 0.012 μm2 area. However, this gate is not suitable for designing large scale circuits. Balali et al., in [19], proposed another 14 cells XOR gate; however, the use of half-cell translation inverter gates make this gate more impractical in terms of physical realization. More recently, Bahar et al., in [20], claimed that the proposed E-shaped XOR gate is capable of achieving higher designing optimization at a more extensive design paradigm. In the following, a unique ultra-efficient XOR gate is proposed. The QCA layout of this gate is simple, efficient and appropriate to design of all logical functions. In addition, **Figure 2** depicts various layouts of previously 3-input XOR gate in QCA presented in the literature.

### **4. The proposed three-input QCA XOR gate**

Exclusive-OR (XOR) is the most fundamental component used in digital circuits including parity generator and checker, comparator, code converter, arithmetic and logic processing unit, and so on. QCA layout of the proposed

**Figure 3.** *The QCA layout of the proposed three-input XOR gate and its power dissipation map.*

three-input XOR gate and its power dissipation map are shown in **Figure 3(a)** and **(b)** respectivly, which consists 12 cells with occupied area is 0.01 μm<sup>2</sup> and requires two clock phases to generate the corrects output. It is clear in the suggested layout that there is no majority gate, resulting in reduced space and energy consumed. In fact, the presented layout utilize electrostatic interactions between cells within QCA configurations to perform desired function.
