*2.1.1 Introduction to dislocations*

The technology of monolithic integration of III-V on Si is of great interest due to combining the superior optical properties of III-V materials and the advantages of Si substrates such as low cost and high scalability [27]. However, as most III-V semiconductor materials have a relative large difference in lattice constant to Si, high density of crystal defects are generated during the epitaxial growth. This leads to the failure of the technique of direct deposition of III/V on Si become commercially viable in 1980s, despite intensive studies have been demonstrated in that era [28]. The lattice mismatch property creates a substantial stress accumulation in the first few pseudomorphic layers of deposited material, as shown in **Figure 10a**. As the stress is accumulated above a critical value of growth thickness, the strainrelaxation process leads the generation of misfit dislocations (MDs). The MDs are associated with missing or dangling bonds along the mismatched interface which are shown in **Figure 10b** [30], thus MDs lie entirely on the growth plane. Since the dislocations cannot be eliminated within a crystal due to energetic reasons, the MDs must either reach the edge of crystal or turn upward through the deposited layers to form TDs. As a result, from the transmission electron microscopy (TEM) shown in **Figure 10c**, TDs seem to extend from the interface of III-V and Si, and go through the epilayer. TDs are likely to be transferred from MDs when the distance to the sample edge is much longer than the distance to the epi-layer surface. Meanwhile, TDs could also transfer to MDs either through dislocation glides, extending the misfit segment beneath it, or in active region during the electron–hole recombination through the phenomenon known as recombination-enhanced dislocations

#### **Figure 10.**

*Schematic change in lattices of thin film on substrates and bright field scanning TEM image of TDs. (a) denoting the initial pseudomorphic layers of deposited materials. (b) denoting MD as spinning "T". (c) a bright-field STEM image showing the TDs. (adapted from Ref. [29]).*

obtained on the buffer with APBs. The μ<sup>e</sup> = 2000 cm2

*layer without APBs. The FWHM of the peak is 40% lower [17].*

**)**

Si(001) Si(001)

Sample Doping

**250 nm GaAs:Si (7 <sup>10</sup><sup>12</sup> cm<sup>3</sup>**

**Active layer without APBs**

**2. Part 2: reduction of threading dislocations density**

on-GaAs in the same reactor.

*higher for the layer without APBs [17].*

**1.3 Summary**

**Table 1.**

**Figure 9.**

*Post-Transition Metals*

**GaAs/Si(100).**

**136**

layer is nearly equivalent to the mobility measured from an homoepitaxy n:GaAs-

*Hall effect measurements at 300 K for GaAs-on-Si layers with/without APBs. The electron mobility is 10 times*

*PL spectra at 300 K for GaAs-on-Si layers with and without APBs. The PL intensity is 3 times higher for the*

**400 nm GaAs buffer With APBs 400 nm GaAs buffer Without**

Electron mobility (cm<sup>2</sup>

V.s)

/

level (cm<sup>3</sup> )

GaAs-on-Si with APB <sup>7</sup> <sup>10</sup><sup>17</sup> <sup>200</sup> <sup>2</sup> <sup>10</sup><sup>2</sup> GaAs-on-Si without APB <sup>7</sup> <sup>10</sup><sup>17</sup> <sup>2000</sup> <sup>4</sup> <sup>10</sup><sup>3</sup> GaAs-on-GaAs <sup>7</sup> <sup>10</sup><sup>17</sup> <sup>2500</sup> <sup>3</sup> <sup>10</sup><sup>3</sup>

**APBs formation during the heteroepitaxy of GaAs on nominal Si(100) substrates has hindered for a long time the development of GaAs devices on a Si CMOS platform. With new technologies and processes established by**

**researchers and tools suppliers to control the atmosphere in growth chambers and prepare the Si surface before the epitaxy, one can get rid of APBs easily on**

The strategies to reduce the threading dislocation density (TDD) in the III-V layer can be classified according to two major tendencies: 1) engineering of thick buffer layer (strained layer superlattices, germanium buffer layer, … ) to annihilate

V<sup>1</sup> s

**VS 250 nm GaAs:Si(7 <sup>10</sup><sup>12</sup> cm<sup>3</sup>**

**Active layer without APBs**

**APBs**

Resistivity (W/cm)

<sup>1</sup> value of the APBs-free

**)**

motion [31]. Typically, in the growth of GaAs on Si, the TDD is around 10<sup>10</sup> cm�<sup>2</sup> at the growth interface [32]. Unfortunately, the viable TDD in active region for practical optoelectronic devices should be below 106 cm�<sup>2</sup> [32], which held back the development of many III-V on Si material systems for some time. Those dislocations have associated trap states serving as nonradiative recombination centers to reduce the photon emission efficiency and/or minority carrier lifetime [32], resulting in a degradation of devices performance. In addition, those states in the band could also increase the leakage current of the devices [3].

However, due to the difference in thermal expansion coefficients of GaAs and Si, a GaAs layer which is thicker than 7 μm will induce micro cracks on GaAs thin films [37]. In addition, a thick GaAs buffer on Si will bend the wafer [34]. Thus, a more effective method known as dislocation filtering has been put forward to induce designed strain to bend the TDs and to encourage TDs to move, interact and annihilate [28]. The most common dislocation filter layer (DFL) system includes strained layer superlattice (SLSs) and quantum-dot (QD) DFL, while different SLS structure including InGaN/GaN [38], InGaAs/GaAs, InAlAs/GaAs [32] and GaAsP/ GaAs [39], have been studied. A typical cross-sectional TEM measurement for InGaAs/GaAs SLSs DFLs is shown in **Figure 12(a)**, indicating how the TDs are eliminated within DFLs. Taking InGaAs/GaAs DFL for example, a layer structure of InGaAs/GaAs is shown in **Figure 12(b)**. The strain direction, induced by the lattice

*GaAs Compounds Heteroepitaxy on Silicon for Opto and Nano Electronic Applications*

The appropriate choice of composition and thickness for SLS is dependent on the material and the prior dislocation density. Since the purpose of DFL structure is to introduce strain to promote the TD motions, forming dislocations should be avoided within DFL, which means the thickness for each layer should below the critical thickness. For most SLSs, the thickness of each layer should below 20 nm [28, 29, 32]. By using SLS DFL technique, researchers from University College London have successfully reduced the TD density down to the 10<sup>6</sup> cm<sup>2</sup> [27]. Although SLSs have been proved to remove more than 90% of TDs [28], the induced strain which bends TDs is still within 2 dimensions. QD is a 0-dimensional nanostructure with much larger strain field compared to SLS. As a result, it is believed that QD can also sever as the DFL, which might be even superior than SLSs [40]. Researchers from University of Michigan have proved that InAs QDs were the most suitable QD. A fabricated laser structure with InAs QD DFL was demonstrated

InxGa1-xAs/GaAs SLSs have been recently studied on the GaAs/Si material platform due to its variable strain force. Since the bending efficiency to TDs depends on the strained induced by the lattice-mismatched, the indium composition, the

*An InGaAs/GaAs DFL schematic structure in different views. (a) The DFL sample structure in the cross-section TEM. (Reproduced from Ref. [28]). (b) The layer structure of 5 layers of SLSs. (c) The DFL structure in lattice*

mismatch, inside the DFL is shown in **Figure 12(c)**.

*DOI: http://dx.doi.org/10.5772/intechopen.94609*

with a threshold current density of 900 Acm<sup>2</sup> [40].

*2.1.2 Validation of SLS DFL*

**Figure 12.**

**139**

*view. The blue arrow denotes the direction of the strain.*

Efforts have been made to control the TDD in GaAs grown on Si substrates. As the thickness of deposited layer increases, TDs will glide, move and react with other TDs depending on their Burger vectors, resulting in a repulsion or annihilation as **Figure 11** shows. As TDs keep propagating in the overlayers, they are likely to meet other dislocations to be self-annihilated as shown in **Figure 11**. If there is a strain induced by the lattice mismatched between the underlayer and overlayer, generated TDs are expected to experience lateral forces which drive TDs into edge as **Figure 11** deflection to edge shows.

The deflection process relives the strain induced by lattice mismatch and makes TDs to react with other TDs more likely and/or convert TDs into MDs to decrease the TDD. As demonstrated by Masami and Masafumi in 1990, the dislocation density n in a thick GaAs layer grown on Si can be estimated through the following Equation [34]:

$$\mathbf{n}(\mathbf{x}) = \frac{1}{\left(\mathbb{1}\nmid\_{\mathbb{D}\_0} + \mathbb{b}\nmid\_{\mathbf{a}}\right) \exp\left(\mathbf{ax}\right) - \mathbb{b}\nmid\_{\mathbf{a}}}$$

where x is the thickness of the GaAs layer, D0 is the dislocation density at the interface, a and b are two constants related to the density of etch pit defects (EPD) and coalescence of dislocations respectively. According to their characterization, D0 = 10<sup>12</sup> cm�<sup>2</sup> ,a=2 � 10 cm�<sup>1</sup> , and b = 1.8 � <sup>10</sup>�<sup>5</sup> cm. For the dislocation density in a thin GaAs film on Si, it can be estimated through n(x) = D0hm, where D0 is the dislocation density at the interface and m is the empirical value with minus symbol [28, 35, 36]. In order to reduce the TDD to the level of 10<sup>6</sup> cm�<sup>2</sup> , the thickness of GaAs is estimated to be as thick as 100 μm [34].

**Figure 11.** *Mechanisms of dislocation motion in GaAs/Si. (Reproduced from Ref. [33]).*

## *GaAs Compounds Heteroepitaxy on Silicon for Opto and Nano Electronic Applications DOI: http://dx.doi.org/10.5772/intechopen.94609*

However, due to the difference in thermal expansion coefficients of GaAs and Si, a GaAs layer which is thicker than 7 μm will induce micro cracks on GaAs thin films [37]. In addition, a thick GaAs buffer on Si will bend the wafer [34]. Thus, a more effective method known as dislocation filtering has been put forward to induce designed strain to bend the TDs and to encourage TDs to move, interact and annihilate [28]. The most common dislocation filter layer (DFL) system includes strained layer superlattice (SLSs) and quantum-dot (QD) DFL, while different SLS structure including InGaN/GaN [38], InGaAs/GaAs, InAlAs/GaAs [32] and GaAsP/ GaAs [39], have been studied. A typical cross-sectional TEM measurement for InGaAs/GaAs SLSs DFLs is shown in **Figure 12(a)**, indicating how the TDs are eliminated within DFLs. Taking InGaAs/GaAs DFL for example, a layer structure of InGaAs/GaAs is shown in **Figure 12(b)**. The strain direction, induced by the lattice mismatch, inside the DFL is shown in **Figure 12(c)**.

The appropriate choice of composition and thickness for SLS is dependent on the material and the prior dislocation density. Since the purpose of DFL structure is to introduce strain to promote the TD motions, forming dislocations should be avoided within DFL, which means the thickness for each layer should below the critical thickness. For most SLSs, the thickness of each layer should below 20 nm [28, 29, 32]. By using SLS DFL technique, researchers from University College London have successfully reduced the TD density down to the 10<sup>6</sup> cm<sup>2</sup> [27].

Although SLSs have been proved to remove more than 90% of TDs [28], the induced strain which bends TDs is still within 2 dimensions. QD is a 0-dimensional nanostructure with much larger strain field compared to SLS. As a result, it is believed that QD can also sever as the DFL, which might be even superior than SLSs [40]. Researchers from University of Michigan have proved that InAs QDs were the most suitable QD. A fabricated laser structure with InAs QD DFL was demonstrated with a threshold current density of 900 Acm<sup>2</sup> [40].

#### *2.1.2 Validation of SLS DFL*

motion [31]. Typically, in the growth of GaAs on Si, the TDD is around 10<sup>10</sup> cm�<sup>2</sup> at the growth interface [32]. Unfortunately, the viable TDD in active region for practical optoelectronic devices should be below 106 cm�<sup>2</sup> [32], which held back the development of many III-V on Si material systems for some time. Those dislocations have associated trap states serving as nonradiative recombination centers to reduce the photon emission efficiency and/or minority carrier lifetime [32], resulting in a degradation of devices performance. In addition, those states in the band could also

Efforts have been made to control the TDD in GaAs grown on Si substrates. As the thickness of deposited layer increases, TDs will glide, move and react with other TDs depending on their Burger vectors, resulting in a repulsion or annihilation as **Figure 11** shows. As TDs keep propagating in the overlayers, they are likely to meet other dislocations to be self-annihilated as shown in **Figure 11**. If there is a strain induced by the lattice mismatched between the underlayer and overlayer, generated

The deflection process relives the strain induced by lattice mismatch and makes TDs to react with other TDs more likely and/or convert TDs into MDs to decrease the TDD. As demonstrated by Masami and Masafumi in 1990, the dislocation density n in a thick GaAs layer grown on Si can be estimated through the following

where x is the thickness of the GaAs layer, D0 is the dislocation density at the interface, a and b are two constants related to the density of etch pit defects (EPD) and coalescence of dislocations respectively. According to their characterization,

in a thin GaAs film on Si, it can be estimated through n(x) = D0hm, where D0 is the dislocation density at the interface and m is the empirical value with minus symbol

*=*a

, and b = 1.8 � <sup>10</sup>�<sup>5</sup> cm. For the dislocation density

, the thickness of

TDs are expected to experience lateral forces which drive TDs into edge as

n xð Þ¼ <sup>1</sup> 1*=*D0 þ <sup>b</sup>*=*a exp ax ð Þ� <sup>b</sup>

[28, 35, 36]. In order to reduce the TDD to the level of 10<sup>6</sup> cm�<sup>2</sup>

*Mechanisms of dislocation motion in GaAs/Si. (Reproduced from Ref. [33]).*

increase the leakage current of the devices [3].

,a=2 � 10 cm�<sup>1</sup>

GaAs is estimated to be as thick as 100 μm [34].

**Figure 11** deflection to edge shows.

Equation [34]:

*Post-Transition Metals*

D0 = 10<sup>12</sup> cm�<sup>2</sup>

**Figure 11.**

**138**

InxGa1-xAs/GaAs SLSs have been recently studied on the GaAs/Si material platform due to its variable strain force. Since the bending efficiency to TDs depends on the strained induced by the lattice-mismatched, the indium composition, the

#### **Figure 12.**

*An InGaAs/GaAs DFL schematic structure in different views. (a) The DFL sample structure in the cross-section TEM. (Reproduced from Ref. [28]). (b) The layer structure of 5 layers of SLSs. (c) The DFL structure in lattice view. The blue arrow denotes the direction of the strain.*

thickness of strained layer, and the repetition of SLSs as well as the DFLs are of the greatest interest and need to be considered when optimizing the SLS.
