**1.1 Silicon surface preparation under H2 ambient**

Considering the thermodynamical models, the double-layer steps formation on nominal Si(001) is predicted as highly unfavorable in ultra-high Vacuum (UHV) or in inert gas ambient. The stress relaxation induced by dimerization of the (2 1)-Si (001) reconstruction promotes single step formation until a miscut angle lying in a range between 1 and 3° [7–10]. Thus, the (001) surface of nominal wafers is made of alternating (2 1) and (1 2)-reconstructed terraces (named A-type and B-type terraces respectively) separated by SA and SB single steps according to the Chadi's nomenclature (**Figure 2**) [8]. For A-type terraces the Si-dimer rows are parallel to the step edges while they are perpendicular for B-type terraces.

The formation energy of the bare line defects DVR and DVL (i.e. with dangling bonds, labelled DVR and DVL no hydrogen), are represented on the **Figure 3b**. In order to take into account the hydrogen of the chamber in CVD ambient, the bare line defects are modified by placing a single hydrogen atom on each silicon of the first bulk layer with a dangling bond (**Figure 3a**), changing their geometry and their formation energies. Indeed, the DFT calculations show that for both defects and whatever the surface states, the geometry distortions of the bare defects are considerably reduced when the defect is hydrogenated. In the DVR case, for instance, the dimers in the line adopt a flat position instead of a tilted one. This reduction in elastic stress is key in the formation energy lowering of the line defects. As shown on **Figure 3b**, for hydrogen rich conditions (right handside of the graph **Figure 3b**), the formation energies of both hydrogenated DVR (H-DVR) and DVL (H-DVL) are lower than for the bare defects. Moreover, two regimes can be observed whatever the surface state is. One range for superhigh H chemical potentials where the H-DVL is favored, and a medium range of H chemical potentials where the H-DVR takes prominence. It is worth to note that the gain in energy per dimer can be quite important (several eVs) when comparing the different ranges, showing that the

*(a) Schematic view of the DVR and DVL line defects on the 2 2 reconstructed silicon surface. Only two silicon bulk layers are represented (black and dark grey) in addition to the surface layer which is reconstructed. The distance from the surface is coded in gray-scale. Silicon atoms marked with a small white disk are hydrogenated in the case of hydrogenated DVR and DVL. (b) The variation of the formation energy of both DVR and DVL*

*defects, bare or hydrogenated with respect to the chemical potential of the hydrogen. From [11].*

*GaAs Compounds Heteroepitaxy on Silicon for Opto and Nano Electronic Applications*

*DOI: http://dx.doi.org/10.5772/intechopen.94609*

The role of hydrogen is thus twofold. It first induces a large increase of dimervacancy concentration due to the lowering of their formation energy. The second effect of hydrogen is to select DVR with respect to DVL when using suitable hydrogen annealing conditions. This latter point is the key to obtain a single domain Si(001) surface. Indeed, the DVRs cross the B-type terraces in a direction perpendicular to the step edges. This can generates a nearly complete etching of the SB steps if the terraces are not too large. This assumption was tested with a 600 Torr/ 900°C/10 min H2 annealing of different on-axis Si(001) wafers. Prior to the H2 annealing, the native oxide is removed by SICONI™ process [14]. Atomic force microscopy (AFM) images of **Figure 4a**. shows the result obtained from a wafer with a very slight 0.05° misorientation near the [110] direction. The DVRs that run across the B-type terraces can be clearly distinguished. They lead to comb-like shaped B-type terraces. Nevertheless, the terrace width is too large (the miscut angle too small) to obtain a complete removal of B-type terraces. On the contrary, when using a wafer with an higher misorientation (0.15°) in the [110] direction, the B-type terraces can be selectively etched as shown in **Figure 4b**. The AFM line profile confirms the formation of double steps (2.7 Å in height)). However, there is still a few small islands remaining at the step edges (not clearly visible from the AFM image). This behavior was also observed by other authors working on

selectivity with respect to H chemical potential is quite strong.

**Figure 3.**

**131**

However, computational modeling highlights a possible mechanism to get a nearly single-domain Si(001) surface by selective etching of SB steps (i.e. by removing the B-type terraces) **under very specific H2 annealing process conditions** [11]. The energy needed for this process to occur has been calculated by using DFT and the most favorable mechanism has been highlighted. For calculation simplification, a Si(001) 2 2 reconstructed surface has been considered, but the conclusions will be transferable to the real case ie. Si(001) 2 1 reconstruction.

The removal of two neighboring silicon atoms from the considered Si(001) surface (**Figure 2**) creates the so-called single-dimer vacancy (SDV) [12]. Line defects on the surface can appear by aligning SDV together, either in lines, creating dimer-vacancy lines (DVL) or in rows creating dimer-vacancy rows (DVR) [13] as shown respectively in green and pink areas of **Figure 3a**.

**Figure 2.**

*Dimerization of the Si(001) surface with alternating (2 1) and (1 2)-reconstructed terraces (named Atype and B-type terraces respectively) separated by SA and SB single steps.*

*GaAs Compounds Heteroepitaxy on Silicon for Opto and Nano Electronic Applications DOI: http://dx.doi.org/10.5772/intechopen.94609*

#### **Figure 3.**

**1.1 Silicon surface preparation under H2 ambient**

**Figure 1.**

**Figure 2.**

**130**

*reference [1].*

*Post-Transition Metals*

the step edges while they are perpendicular for B-type terraces.

shown respectively in green and pink areas of **Figure 3a**.

*type and B-type terraces respectively) separated by SA and SB single steps.*

Considering the thermodynamical models, the double-layer steps formation on nominal Si(001) is predicted as highly unfavorable in ultra-high Vacuum (UHV) or in inert gas ambient. The stress relaxation induced by dimerization of the (2 1)-Si (001) reconstruction promotes single step formation until a miscut angle lying in a range between 1 and 3° [7–10]. Thus, the (001) surface of nominal wafers is made of alternating (2 1) and (1 2)-reconstructed terraces (named A-type and B-type terraces respectively) separated by SA and SB single steps according to the Chadi's nomenclature (**Figure 2**) [8]. For A-type terraces the Si-dimer rows are parallel to

*Ball-and-stick model of III-V-on-Si with {110} and {111}-APBs. The single-layer step edges initiate the formation of the APBs while the surface with double-layer steps allows a single-domain III-V cristal. From*

However, computational modeling highlights a possible mechanism to get a nearly single-domain Si(001) surface by selective etching of SB steps (i.e. by removing the B-type terraces) **under very specific H2 annealing process conditions** [11]. The energy needed for this process to occur has been calculated by using DFT and the most favorable mechanism has been highlighted. For calculation simplification, a Si(001) 2 2 reconstructed surface has been considered, but the conclusions will be transferable to the real case ie. Si(001) 2 1 reconstruction. The removal of two neighboring silicon atoms from the considered Si(001) surface (**Figure 2**) creates the so-called single-dimer vacancy (SDV) [12]. Line defects on the surface can appear by aligning SDV together, either in lines, creating dimer-vacancy lines (DVL) or in rows creating dimer-vacancy rows (DVR) [13] as

*Dimerization of the Si(001) surface with alternating (2 1) and (1 2)-reconstructed terraces (named A-*

*(a) Schematic view of the DVR and DVL line defects on the 2 2 reconstructed silicon surface. Only two silicon bulk layers are represented (black and dark grey) in addition to the surface layer which is reconstructed. The distance from the surface is coded in gray-scale. Silicon atoms marked with a small white disk are hydrogenated in the case of hydrogenated DVR and DVL. (b) The variation of the formation energy of both DVR and DVL defects, bare or hydrogenated with respect to the chemical potential of the hydrogen. From [11].*

The formation energy of the bare line defects DVR and DVL (i.e. with dangling bonds, labelled DVR and DVL no hydrogen), are represented on the **Figure 3b**. In order to take into account the hydrogen of the chamber in CVD ambient, the bare line defects are modified by placing a single hydrogen atom on each silicon of the first bulk layer with a dangling bond (**Figure 3a**), changing their geometry and their formation energies. Indeed, the DFT calculations show that for both defects and whatever the surface states, the geometry distortions of the bare defects are considerably reduced when the defect is hydrogenated. In the DVR case, for instance, the dimers in the line adopt a flat position instead of a tilted one. This reduction in elastic stress is key in the formation energy lowering of the line defects. As shown on **Figure 3b**, for hydrogen rich conditions (right handside of the graph **Figure 3b**), the formation energies of both hydrogenated DVR (H-DVR) and DVL (H-DVL) are lower than for the bare defects. Moreover, two regimes can be observed whatever the surface state is. One range for superhigh H chemical potentials where the H-DVL is favored, and a medium range of H chemical potentials where the H-DVR takes prominence. It is worth to note that the gain in energy per dimer can be quite important (several eVs) when comparing the different ranges, showing that the selectivity with respect to H chemical potential is quite strong.

The role of hydrogen is thus twofold. It first induces a large increase of dimervacancy concentration due to the lowering of their formation energy. The second effect of hydrogen is to select DVR with respect to DVL when using suitable hydrogen annealing conditions. This latter point is the key to obtain a single domain Si(001) surface. Indeed, the DVRs cross the B-type terraces in a direction perpendicular to the step edges. This can generates a nearly complete etching of the SB steps if the terraces are not too large. This assumption was tested with a 600 Torr/ 900°C/10 min H2 annealing of different on-axis Si(001) wafers. Prior to the H2 annealing, the native oxide is removed by SICONI™ process [14]. Atomic force microscopy (AFM) images of **Figure 4a**. shows the result obtained from a wafer with a very slight 0.05° misorientation near the [110] direction. The DVRs that run across the B-type terraces can be clearly distinguished. They lead to comb-like shaped B-type terraces. Nevertheless, the terrace width is too large (the miscut angle too small) to obtain a complete removal of B-type terraces. On the contrary, when using a wafer with an higher misorientation (0.15°) in the [110] direction, the B-type terraces can be selectively etched as shown in **Figure 4b**. The AFM line profile confirms the formation of double steps (2.7 Å in height)). However, there is still a few small islands remaining at the step edges (not clearly visible from the AFM image). This behavior was also observed by other authors working on

**Figure 4.**

*<sup>2</sup> <sup>2</sup> <sup>μ</sup>m2 AFM image of nominal Si(001) surfaces after 600 Torr/900°C/10 min H2 annealing (a) substrate 0.05° misoriented near [110]. DVRs crosse the B-type (A-type) terraces in a direction perpendicular (parallel) to the single-step edges (b) substrate 0.15° misoriented in [110]. The surface is double-stepped with terraces width of 100 nm and step height of 2.7 Å (line profile in inset). (c) substrate 0.12° misoriented near [100]. H-DVRs lead to dendritic single-steps oriented in <110> directions. Images partially reproduced from [11].*

is shown in **Figure 5b**. The surface roughness is improved and the RMS value drop to 0.8 nm. This roughness is similar to the one reported for 1 μm thick GaAs grown on 4°-6° offcut Si(001) substrate [18–20], despite the fact that only 150 nm of GaAs were grown. No V-groove feature is observed indicating that a APBs-free surface is formed. The absence of APBs on top of the GaAs layer is confirmed by the STEM cross section image (inset of **Figure 5b**.). The (110)-STEM cross-section shows a dark zone at the bottom of the GaAs layer due to the highly defective Si/GaAs heterointerface. The defective area is a combination of multiple crystalline defects

*<sup>5</sup> <sup>5</sup> <sup>μ</sup>m2 AFM images of (a) 400 nm-thick GaAs epitaxially grown on 0.05°-miscut angle Si(001) wafer: High density of randomly oriented APBs. RMS roughness = 1.7 nm. (b) 150 nm-thick epitaxially grown APBsfree GaAs on Si(001) wafer with a 0.15°-miscut angle toward the [110]. The (110)-STEM cross section in inset shows a layer free of APBs beyond about 70 nm of thickness. (c) APBs-free GaAs film grown on Si wafer with a > 0.1°-misorientation toward a random direction. In this case, 300-400 nm of thickness is necessary to*

*GaAs Compounds Heteroepitaxy on Silicon for Opto and Nano Electronic Applications*

Interestingly, a GaAs film grown on Si wafer with a misorientation above 0.1° and toward a random direction (different from the <110>) is also APBs-free beyond a thickness of about 300-400 nm (**Figure 5c**). This can be achieved even though the Si surface is only made of single-layer steps. Actually, this silicon surface, described in the previous section and in **Figure 4c**, is made of very narrow dendritic terraces. Thus, the (2 1)/(1 2)-Si domains size are small enough to enable the self-annihilation of the APBs. However, when the misorientation is not in the <110>, a 100 nm-thick GaAs layer is not sufficient to get rid of the APBs and a

In an industrial point of view, this is particularly important to relax the constraint on the wafer miscut specifications. Any substrate with a miscut-angle >0.1° can be used whatever the in-plane direction of the wafer slicing. Therefore, contrary to the GaP-on-Si system, the double-layer steps on nominal silicon wafers is

such as dislocations, stacking faults and APBs due to the remaining small monoatomic silicon islands mentioned before. However, for a thickness beyond about 70 nm, no more APB planes propagate toward the surface. Indeed, the APB planes that nucleate at these monoatomic step edges have intersected pairwise during the high temperature growth and thus self-annihilated. The kinking of APBs in the III-V layers followed by their self-annihilation is often explained by kinetic phenomena [21, 22]. In such mechanisms, the adatoms incorporation rate is anisotropic along the two azimuthal <110> directions. In GaAs, several groups have indeed already shown a diffusion constant of Ga atoms 4 times larger along the As dimer lines regarding to the one along the dimer rows [23–25]. It results in a bias between the growth rate of the domains in antiphase responsible for the kinking of

*get rid of APBs. Images partially reproduced from [11, 17].*

*DOI: http://dx.doi.org/10.5772/intechopen.94609*

the APBs.

**133**

**Figure 5.**

thicker buffer layer is required.

not mandatory to achieve a APBs-free GaAs layer.

GaP-on-Si growth [15, 16]. H2 annealing of a Si(001) substrate with a 0.12° miscut near the [100] direction was also tested. When the miscut direction slightly differs from the <110> azimuthal directions, each terrace boundary is made of two types of step edge (with both SA and SB steps). The selective etching of the SB-segments leads to a dendritic shape of the terraces (**Figure 4c**). Thus, it is not possible to achieve double-layer steps formation on wafers having a miscut direction different from <110>. It should also be noted that the SB step etching only occurs for hydrogen conditions near the atmospheric pressure and for a temperature > 850°C [11]. Otherwise, the generation of dimer-vacancies agglomeration is energetically not favorable for such hydrogen chemical potential (**Figure 3b**).

#### **1.2 APBs-free GaAs growth on Si(001)**

The effectiveness of the Si surface preparation for APBs removal was proven from GaAs growth on different types of nominal wafers. MOCVD growth of GaAs-on-Si can be achieved using a two-step process [4, 5]: few nanometers of a high-density nucleation layer is first deposited at low temperature (350–450°C) followed by the coalescence of the nuclei during temperature ramp up to 550–700°C. Then at this temperature, a thicker GaAs layer is epitaxially grown to improve the material quality. Classical group-III precursors are TMGa or TEGa while group-V precursors are often TBAs or AsH3 for the high temperature step. The precursors are injected in the MOCVD chamber using purified H2 as carrier gas. **Figure 5a** shows the morphology of the GaAs surface grown on Si wafer with miscut angle <0,1° (the type of Si surface presented in **Figure 4a**). Thanks to their V groove shapes, randomly oriented APBs can be observed by AFM with a linear density of several μm<sup>1</sup> . This APB density is equivalent to the one obtain for a GaAs growth on a silicon substrate without any surface preparation. It results in a large surface roughness with a root mean square (RMS) value of about 1.5–2 nm. As mentioned before, the APBs originate at the single-step edges between the very large (2 1)/(1 2)-Si(001) terraces of **Figure 4a**. Thus, the self-annihilation of the APBs is not possible in the GaAs layer (with a typical thickness around 400 nm) due to the large inter-APB distance.

As the Si wafer miscut angle is increased above 0.1° exactly in the [110] direction, the APBs can be easily removed. The AFM image of a 150 nm thick GaAs layer *GaAs Compounds Heteroepitaxy on Silicon for Opto and Nano Electronic Applications DOI: http://dx.doi.org/10.5772/intechopen.94609*

#### **Figure 5.**

GaP-on-Si growth [15, 16]. H2 annealing of a Si(001) substrate with a 0.12° miscut near the [100] direction was also tested. When the miscut direction slightly differs from the <110> azimuthal directions, each terrace boundary is made of two types of step edge (with both SA and SB steps). The selective etching of the SB-segments leads to a dendritic shape of the terraces (**Figure 4c**). Thus, it is not possible to achieve double-layer steps formation on wafers having a miscut direction different from <110>. It should also be noted that the SB step etching only occurs for hydrogen conditions near the atmospheric pressure and for a temperature > 850°C [11]. Otherwise, the generation of dimer-vacancies agglomeration is energetically

*<sup>2</sup> <sup>2</sup> <sup>μ</sup>m2 AFM image of nominal Si(001) surfaces after 600 Torr/900°C/10 min H2 annealing (a) substrate 0.05° misoriented near [110]. DVRs crosse the B-type (A-type) terraces in a direction perpendicular (parallel) to the single-step edges (b) substrate 0.15° misoriented in [110]. The surface is double-stepped with terraces width of 100 nm and step height of 2.7 Å (line profile in inset). (c) substrate 0.12° misoriented near [100]. H-DVRs lead to dendritic single-steps oriented in <110> directions. Images partially reproduced from [11].*

The effectiveness of the Si surface preparation for APBs removal was proven from GaAs growth on different types of nominal wafers. MOCVD growth of GaAs-on-Si can be achieved using a two-step process [4, 5]: few nanometers of a high-density nucleation layer is first deposited at low temperature (350–450°C) followed by the coalescence of the nuclei during temperature ramp up to 550–700°C. Then at this temperature, a thicker GaAs layer is epitaxially grown to improve the material quality. Classical group-III precursors are TMGa or TEGa while group-V precursors are often TBAs or AsH3 for the high temperature step. The precursors are injected in the MOCVD chamber using purified H2 as carrier gas. **Figure 5a** shows the morphology of the GaAs surface grown on Si wafer with miscut angle <0,1° (the type of Si surface presented in **Figure 4a**). Thanks to their V groove shapes, randomly oriented APBs

. This APB density is

not favorable for such hydrogen chemical potential (**Figure 3b**).

can be observed by AFM with a linear density of several μm<sup>1</sup>

equivalent to the one obtain for a GaAs growth on a silicon substrate without any surface preparation. It results in a large surface roughness with a root mean square (RMS) value of about 1.5–2 nm. As mentioned before, the APBs originate at the single-step edges between the very large (2 1)/(1 2)-Si(001) terraces of **Figure 4a**. Thus, the self-annihilation of the APBs is not possible in the GaAs layer (with a typical thickness around 400 nm) due to the large inter-APB distance.

As the Si wafer miscut angle is increased above 0.1° exactly in the [110] direction, the APBs can be easily removed. The AFM image of a 150 nm thick GaAs layer

**1.2 APBs-free GaAs growth on Si(001)**

**Figure 4.**

*Post-Transition Metals*

**132**

*<sup>5</sup> <sup>5</sup> <sup>μ</sup>m2 AFM images of (a) 400 nm-thick GaAs epitaxially grown on 0.05°-miscut angle Si(001) wafer: High density of randomly oriented APBs. RMS roughness = 1.7 nm. (b) 150 nm-thick epitaxially grown APBsfree GaAs on Si(001) wafer with a 0.15°-miscut angle toward the [110]. The (110)-STEM cross section in inset shows a layer free of APBs beyond about 70 nm of thickness. (c) APBs-free GaAs film grown on Si wafer with a > 0.1°-misorientation toward a random direction. In this case, 300-400 nm of thickness is necessary to get rid of APBs. Images partially reproduced from [11, 17].*

is shown in **Figure 5b**. The surface roughness is improved and the RMS value drop to 0.8 nm. This roughness is similar to the one reported for 1 μm thick GaAs grown on 4°-6° offcut Si(001) substrate [18–20], despite the fact that only 150 nm of GaAs were grown. No V-groove feature is observed indicating that a APBs-free surface is formed. The absence of APBs on top of the GaAs layer is confirmed by the STEM cross section image (inset of **Figure 5b**.). The (110)-STEM cross-section shows a dark zone at the bottom of the GaAs layer due to the highly defective Si/GaAs heterointerface. The defective area is a combination of multiple crystalline defects such as dislocations, stacking faults and APBs due to the remaining small monoatomic silicon islands mentioned before. However, for a thickness beyond about 70 nm, no more APB planes propagate toward the surface. Indeed, the APB planes that nucleate at these monoatomic step edges have intersected pairwise during the high temperature growth and thus self-annihilated. The kinking of APBs in the III-V layers followed by their self-annihilation is often explained by kinetic phenomena [21, 22]. In such mechanisms, the adatoms incorporation rate is anisotropic along the two azimuthal <110> directions. In GaAs, several groups have indeed already shown a diffusion constant of Ga atoms 4 times larger along the As dimer lines regarding to the one along the dimer rows [23–25]. It results in a bias between the growth rate of the domains in antiphase responsible for the kinking of the APBs.

Interestingly, a GaAs film grown on Si wafer with a misorientation above 0.1° and toward a random direction (different from the <110>) is also APBs-free beyond a thickness of about 300-400 nm (**Figure 5c**). This can be achieved even though the Si surface is only made of single-layer steps. Actually, this silicon surface, described in the previous section and in **Figure 4c**, is made of very narrow dendritic terraces. Thus, the (2 1)/(1 2)-Si domains size are small enough to enable the self-annihilation of the APBs. However, when the misorientation is not in the <110>, a 100 nm-thick GaAs layer is not sufficient to get rid of the APBs and a thicker buffer layer is required.

In an industrial point of view, this is particularly important to relax the constraint on the wafer miscut specifications. Any substrate with a miscut-angle >0.1° can be used whatever the in-plane direction of the wafer slicing. Therefore, contrary to the GaP-on-Si system, the double-layer steps on nominal silicon wafers is not mandatory to achieve a APBs-free GaAs layer.

In the same fashion, the GaAs layer can be epitaxially grown by using a latticematched Germanium buffer layer [26]. Beyond the APBs issue, using a relaxed Ge buffer layer is also an interesting strategy to decrease the threading dislocation density in the GaAs layer, as we will see in the next paragraph. Due to the fact that GaAs will be quasi-lattice matched to the Ge strain relaxed buffer and thanks to a reuse of the existing threading dislocations to create new misfit sements if needed, the GaAs/Ge interface should exhibit no such high density of defects as when growing directly GaAs on Si. This will permit a clearer view of the GaAs/Ge interface to precisely observe the defects present when growing polar material on Ge, which is not possible when growing GaAs directly on Si.

<sup>5</sup> <sup>5</sup> <sup>μ</sup>m<sup>2</sup> AFM images (**Figure 6**) show the surface of 300 nm thick GaAs layers grown on 1 μm-thick Ge/Si(001) substrates with three different offcut angles in the <110> direction: (a) 0.1°, (b) 0.3°, and(c) 0.5°. The APBs density decrease as function of the miscut angle. With a silicon wafer having a miscut angle of 0.5° the 300 nm-thick GaAs layer is completely free of APBs.

Contrary to the direct growth of GaAs on Si, we still observe APBs with a 0.3° offcut Si substrate.

In order to have insight on the defects at the interface in this case, crosssectional TEM images of a GaAs layer grown on Ge-buffered Si substrate with a 0.5° offcut in the <110> direction are shown in **Figure 7**. The left hand image shows the overall stack, with (from bottom to top) the 0.5° offcut silicon substrate, the 800 nm thick Ge strain relaxed buffer and the 280 nm thick GaAs layer. The interface between GaAs and Ge is highlighted by a thin white line superimposed in the left hand part of the image. No APBs nucleating at this interface are observed, but some dark dots are nevertheless present. The image in the right hand part of **Figure 5** is a magnified view of this interface, showing randomly distributed, different size dark dots which are small (<50 nm), and not at the origin of any extended defects.

Higher resolution images of two of these interface defects have shown that dark spots at the interface are voids, not APBs. Therefore, we observe no APB when using a 0.5° offcut Si substrate for growing GaAs with an intermediate Ge strain relaxed buffer. This hints that bi-atomic steps are achieved at the surface of the Ge strain relaxed buffer using the appropriate hydrogen bake (T > 750°C at 80 Torr H2), and we observe no APB annihilation such a seen previously when growing GaAs directly on Si.

The progressive improvement of the GaAs layer quality as function of the Si-miscut angle can also be observed from the FWHM of the (004) diffraction line in XRD *ω*-scan (**Figure 8**).

> Detrimental influence of APBs on the optical properties is highlighted from photoluminescence (PL) measurements at 300 K [17]. PL spectra of **Figure 9** compares the near band edge luminescence (1,42 eV) of GaAs-on-Si layers with and

> *High resolution, X-ray diffraction profiles around the (004) order (in the triple axis configuration) for a GaAs layer grown on a Ge-buffered silicon substrate with a 0.1° (solid line), 0.3° (dashed line), and 0.5° (dotted*

> *Cross-sectional TEM images of a GaAs layer on a Ge-buffered Si substrate. The left hand image is an overview of the overall stack, with the 0.5° offcut Si substrate at the bottom. The right hand image is a zoom of the GaAs/*

*GaAs Compounds Heteroepitaxy on Silicon for Opto and Nano Electronic Applications*

*DOI: http://dx.doi.org/10.5772/intechopen.94609*

APBs-free GaAs film is three times higher than the one of the GaAs layer with APBs. Furthermore, the PL peak of the APBs-free is 40% narrower. These results are directly correlated to the role of APBs acting as non-radiative recombination

In the same way, the influence of APBs on the electrical properties is highlighted from the Hall effect measurements on a 250 nm-thick GaAs active layer n-doped at

. This n-doped active layer is grown on intrinsic GaAs-on-Si buffer layers with/without APBs. Hall effect measurements, in the Van der Pauw configuration, are performed by taking 5 points across the whole 300 mm wafer. The mean electron mobilities are reported in **Table 1**. The electron mobility (μe) of the GaAs active layer grown on the APBs-free buffer layer is one decade higher than the one

. The PL intensity of the

without APBs. Both layers are n-doped at 7.10<sup>17</sup> cm<sup>3</sup>

centers.

**135**

**Figure 8.**

*line) offcut. From [26].*

**Figure 7.**

*Ge interface.*

7.10<sup>17</sup> cm<sup>3</sup>

#### **Figure 6.**

*<sup>5</sup> <sup>5</sup> <sup>μ</sup>m2 AFM images of the surface of GaAs layers grown on Ge-buffered silicon(001) substrates with three different offcut angles: (a) 0.1°-offcut angle, (b) 0.3°-offcut angle, and (c) 0.5°- offcut angle. All the offcut angles are in the <110> direction. The scale on the right hand side of each image is labeled in nm. The table (d) presents the APB density measured for each sample. AFM image sides are along the <100> directions. From [26].*

*GaAs Compounds Heteroepitaxy on Silicon for Opto and Nano Electronic Applications DOI: http://dx.doi.org/10.5772/intechopen.94609*

#### **Figure 7.**

In the same fashion, the GaAs layer can be epitaxially grown by using a latticematched Germanium buffer layer [26]. Beyond the APBs issue, using a relaxed Ge buffer layer is also an interesting strategy to decrease the threading dislocation density in the GaAs layer, as we will see in the next paragraph. Due to the fact that GaAs will be quasi-lattice matched to the Ge strain relaxed buffer and thanks to a reuse of the existing threading dislocations to create new misfit sements if needed, the GaAs/Ge interface should exhibit no such high density of defects as when growing directly GaAs on Si. This will permit a clearer view of the GaAs/Ge interface to precisely observe the defects present when growing polar material on Ge,

<sup>5</sup> <sup>5</sup> <sup>μ</sup>m<sup>2</sup> AFM images (**Figure 6**) show the surface of 300 nm thick GaAs layers grown on 1 μm-thick Ge/Si(001) substrates with three different offcut angles in the <110> direction: (a) 0.1°, (b) 0.3°, and(c) 0.5°. The APBs density decrease as function of the miscut angle. With a silicon wafer having a miscut angle of 0.5° the

Contrary to the direct growth of GaAs on Si, we still observe APBs with a 0.3°

Higher resolution images of two of these interface defects have shown that dark

spots at the interface are voids, not APBs. Therefore, we observe no APB when using a 0.5° offcut Si substrate for growing GaAs with an intermediate Ge strain relaxed buffer. This hints that bi-atomic steps are achieved at the surface of the Ge strain relaxed buffer using the appropriate hydrogen bake (T > 750°C at 80 Torr H2), and we observe no APB annihilation such a seen previously when growing

The progressive improvement of the GaAs layer quality as function of the Si-miscut angle can also be observed from the FWHM of the (004) diffraction line

*<sup>5</sup> <sup>5</sup> <sup>μ</sup>m2 AFM images of the surface of GaAs layers grown on Ge-buffered silicon(001) substrates with three different offcut angles: (a) 0.1°-offcut angle, (b) 0.3°-offcut angle, and (c) 0.5°- offcut angle. All the offcut angles are in the <110> direction. The scale on the right hand side of each image is labeled in nm. The table (d) presents the APB density measured for each sample. AFM image sides are along the <100> directions.*

In order to have insight on the defects at the interface in this case, crosssectional TEM images of a GaAs layer grown on Ge-buffered Si substrate with a 0.5° offcut in the <110> direction are shown in **Figure 7**. The left hand image shows the overall stack, with (from bottom to top) the 0.5° offcut silicon substrate, the 800 nm thick Ge strain relaxed buffer and the 280 nm thick GaAs layer. The interface between GaAs and Ge is highlighted by a thin white line superimposed in the left hand part of the image. No APBs nucleating at this interface are observed, but some dark dots are nevertheless present. The image in the right hand part of **Figure 5** is a magnified view of this interface, showing randomly distributed, different size dark dots which are small (<50 nm), and not at the origin of any

which is not possible when growing GaAs directly on Si.

300 nm-thick GaAs layer is completely free of APBs.

offcut Si substrate.

*Post-Transition Metals*

extended defects.

GaAs directly on Si.

**Figure 6.**

*From [26].*

**134**

in XRD *ω*-scan (**Figure 8**).

*Cross-sectional TEM images of a GaAs layer on a Ge-buffered Si substrate. The left hand image is an overview of the overall stack, with the 0.5° offcut Si substrate at the bottom. The right hand image is a zoom of the GaAs/ Ge interface.*

#### **Figure 8.**

*High resolution, X-ray diffraction profiles around the (004) order (in the triple axis configuration) for a GaAs layer grown on a Ge-buffered silicon substrate with a 0.1° (solid line), 0.3° (dashed line), and 0.5° (dotted line) offcut. From [26].*

Detrimental influence of APBs on the optical properties is highlighted from photoluminescence (PL) measurements at 300 K [17]. PL spectra of **Figure 9** compares the near band edge luminescence (1,42 eV) of GaAs-on-Si layers with and without APBs. Both layers are n-doped at 7.10<sup>17</sup> cm<sup>3</sup> . The PL intensity of the APBs-free GaAs film is three times higher than the one of the GaAs layer with APBs. Furthermore, the PL peak of the APBs-free is 40% narrower. These results are directly correlated to the role of APBs acting as non-radiative recombination centers.

In the same way, the influence of APBs on the electrical properties is highlighted from the Hall effect measurements on a 250 nm-thick GaAs active layer n-doped at 7.10<sup>17</sup> cm<sup>3</sup> . This n-doped active layer is grown on intrinsic GaAs-on-Si buffer layers with/without APBs. Hall effect measurements, in the Van der Pauw configuration, are performed by taking 5 points across the whole 300 mm wafer. The mean electron mobilities are reported in **Table 1**. The electron mobility (μe) of the GaAs active layer grown on the APBs-free buffer layer is one decade higher than the one

the defects before growth of the III-V active layer. 2) Selective area epitaxy in dielectric cavities (SiO2,SiN, … ) formed by standard technological steps (deposition, lithography, etching, … ). In this last approach, the threading dislocation (TD) propagation is geometrically limited in one direction by the sidewalls of the patterns. These two majors will be described more deeply in the following paragraphs.

*GaAs Compounds Heteroepitaxy on Silicon for Opto and Nano Electronic Applications*

The technology of monolithic integration of III-V on Si is of great interest due to combining the superior optical properties of III-V materials and the advantages of Si substrates such as low cost and high scalability [27]. However, as most III-V semiconductor materials have a relative large difference in lattice constant to Si, high density of crystal defects are generated during the epitaxial growth. This leads to the failure of the technique of direct deposition of III/V on Si become commercially viable in 1980s, despite intensive studies have been demonstrated in that era [28]. The lattice mismatch property creates a substantial stress accumulation in the first few pseudomorphic layers of deposited material, as shown in **Figure 10a**. As the stress is accumulated above a critical value of growth thickness, the strainrelaxation process leads the generation of misfit dislocations (MDs). The MDs are associated with missing or dangling bonds along the mismatched interface which are shown in **Figure 10b** [30], thus MDs lie entirely on the growth plane. Since the dislocations cannot be eliminated within a crystal due to energetic reasons, the MDs must either reach the edge of crystal or turn upward through the deposited layers to form TDs. As a result, from the transmission electron microscopy (TEM) shown in **Figure 10c**, TDs seem to extend from the interface of III-V and Si, and go through the epilayer. TDs are likely to be transferred from MDs when the distance to the sample edge is much longer than the distance to the epi-layer surface. Meanwhile, TDs could also transfer to MDs either through dislocation glides, extending the misfit segment beneath it, or in active region during the electron–hole recombination through the phenomenon known as recombination-enhanced dislocations

*Schematic change in lattices of thin film on substrates and bright field scanning TEM image of TDs. (a) denoting the initial pseudomorphic layers of deposited materials. (b) denoting MD as spinning "T". (c) a*

*bright-field STEM image showing the TDs. (adapted from Ref. [29]).*

**2.1 Insertion of dislocation filters**

*DOI: http://dx.doi.org/10.5772/intechopen.94609*

*2.1.1 Introduction to dislocations*

**Figure 10.**

**137**

#### **Figure 9.**

*PL spectra at 300 K for GaAs-on-Si layers with and without APBs. The PL intensity is 3 times higher for the layer without APBs. The FWHM of the peak is 40% lower [17].*


#### **Table 1.**

*Hall effect measurements at 300 K for GaAs-on-Si layers with/without APBs. The electron mobility is 10 times higher for the layer without APBs [17].*

obtained on the buffer with APBs. The μ<sup>e</sup> = 2000 cm2 V<sup>1</sup> s <sup>1</sup> value of the APBs-free layer is nearly equivalent to the mobility measured from an homoepitaxy n:GaAson-GaAs in the same reactor.

### **1.3 Summary**

**APBs formation during the heteroepitaxy of GaAs on nominal Si(100) substrates has hindered for a long time the development of GaAs devices on a Si CMOS platform. With new technologies and processes established by researchers and tools suppliers to control the atmosphere in growth chambers and prepare the Si surface before the epitaxy, one can get rid of APBs easily on GaAs/Si(100).**
