**Conclusion**

In the past 30 years, efforts have been made to decrease the TDs induced by the lattice mismatch between GaAs and Si. Many researchers have successfully adopted DFL method to decrease the density of TD to 2 <sup>10</sup><sup>6</sup> cm<sup>2</sup> [45, 50]. However, a 9 μm thick GaAs buffer is indispensable if no other technique applied to achieve that density. Thus, the DFL technique is much more effective in reducing TDs comparing to grow GaAs buffer, which is summarized in **Table 4**.

With the DFL technique, researchers make it possible to reduce the vast number of TDs to a level which is commercially viable in a thin film around 2.5 μm. This


**Table 4.**

*Summary of the requisite thickness with different methods to reduce the density of TD to 2 <sup>10</sup><sup>6</sup> cm<sup>2</sup> .* *GaAs Compounds Heteroepitaxy on Silicon for Opto and Nano Electronic Applications DOI: http://dx.doi.org/10.5772/intechopen.94609*

technique has promoted the implement of III-V materials directly grown on Si such as growth of III-V lasers on Si substrates [27, 50].

### **2.2 GaAs growth on Germanium strain relaxed buffer**

As germanium material has lattice parameter and thermal expansion coefficient close to those of the GaAs, a common strategy is to benefit from all the Ge heteroepitaxy on silicon developments to reduce the structural defects in the GaAs layer [31, 41, 51–53]. This way, we avoid additional threading dislocation nucleation. Currently, the TDD in a 1.5 μm thick Ge-buffer on Si(100) is in the 10<sup>7</sup> cm<sup>2</sup> range by using [54, 55] a thermal cycle annealing (TCA). The **Figure 19a**, extract from the works of Bogumilowicz et al. [56], shows the TDD evolution in function of the Ge buffer and GaAs total thickness, with a GaAs layer fixed at 270 nm thick. The GaAs layer is smooth (<1 nm RMS) and free of APBs thanks to the process described in the previous section. The TDD was estimated by using three methods: (i) from the XRD rocking curve width, the value is extracted with the Ayer's model [57] (ii) by counting the dark spots on the cathodoluminescence (CL) image of the GaAs surface, (iii) by counting the pits on the AFM image of the GaAs surface. Whatever the method, the authors show that the TDD tends to reach a plateau at a value around 3 <sup>10</sup><sup>7</sup> cm<sup>2</sup> . Nevertheless, the downside of the Ge virtual substrate method is the wafer bowing due to the difference between the thermal expansion coefficients (around 120% for Ge and Si). The **Figure 19b** is a plot of the 300 mm wafer bow versus the film thickness. For the thickest Ge buffer layer (1.38 μm) the bow is measured at 240 μm. Such a value is still a hurdle for the wafer handling and processing with the 200/300 mm foundry tools.

#### **2.3 TDD reduction by selective area growth**

Selective growth method is often used in heteroepitaxy of semiconductors where cavities are used to block geometrically the propagation of structural defects that generate at the interface of lattice mismatch semiconductors. Different techniques could be implemented such as Epitaxial Lateral Overgrowth (ELOG) and Aspect Ratio Trapping (ART). We will describe more in details the last one.

ART allows to block inside the cavities some of the threading dislocations and planar defects propagating perpendicularly to the trench direction. Still, a few structural defects propagate through the film. **Figure 20a** summarizes the principle

#### **Figure 19.**

that the QD DFL can bend 60° mixed TDs effectively. In addition, pure edge TDs, which cannot be blocked by the 2-D SLS [49], can be terminated within the QD DFL. Although the detail of this termination is not fully understood, it is believed that the formation of a dislocation loop or the annihilation with a dislocation with reverse Burger's vector result in the termination [48]. Recently, with the help InAs QD DFL, J. Wang et al. demonstrated a low dislocation density of 2 <sup>10</sup><sup>6</sup> cm<sup>2</sup>

*Cross-section TEM images of dislocation propagation in the ten-layers InAs QD with various diffraction*

*conditions: (a) g = [2,*2*,0], (b) g = [1,*1*,1], (c) g = [0,0,4]. (Reproduced from Ref. [48]).*

*GaAs grown on Si with 10 InAs QD layer as dislocation filter. (reproduced from Ref. [48]).*

In the past 30 years, efforts have been made to decrease the TDs induced by the lattice mismatch between GaAs and Si. Many researchers have successfully adopted DFL method to decrease the density of TD to 2 <sup>10</sup><sup>6</sup> cm<sup>2</sup> [45, 50]. However, a 9 μm thick GaAs buffer is indispensable if no other technique applied to achieve that density. Thus, the DFL technique is much more effective in reducing TDs compar-

With the DFL technique, researchers make it possible to reduce the vast number of TDs to a level which is commercially viable in a thin film around 2.5 μm. This

**Technique Thickness** Thick GaAs buffer layer 9 μm InAlAs/GaAs SLSs as DFL 2.35 μm InAs QD as DFL 2.205 μm

*Summary of the requisite thickness with different methods to reduce the density of TD to 2 <sup>10</sup><sup>6</sup> cm<sup>2</sup>*

*.*

[50], with a high efficiency of 96% calculated.

ing to grow GaAs buffer, which is summarized in **Table 4**.

**Conclusion**

**Table 4.**

**144**

**Figure 17.**

*Post-Transition Metals*

**Figure 18.**

*(a) Plot of the TDD in the GaAs overlayers as a function of the total Ge + GaAs thickness. The light gray area corresponds to the expected TDD values in Ge or GaAs single layers as a function of thickness. Estimated error bars are shown for the TDD extracted from AFM and CL. The TDD error bar for the XRD data is* 107*cm*<sup>2</sup>*. (b) Plot of the substrate bow versus the total Ge + GaAs thickness.*

of the method. In fact, the TDs propagating through the dense {111}-planes can be blocked by the geometry of the patterns. In this case the aspect ratio (height on width *h=l* ) of the pattern must be such that *h=<sup>l</sup>*≥ *tan θ*ð Þ <sup>111</sup> ¼ tan 54 ð Þ¼ *:*7° 1*:*4. Therefore, for example, with a 150-thick dielectric, the cavity must be no wider than �100 nm. Nevertheless, as we can see on the figure, the planar defects which lie parallel to the trenches can be more difficult (or impossible) to trap.

In the example of ART from the works of Lau et al. [58], they use about 100 nmwidth oxide trenches on Si(001) etched by a wet solution of KOH to form a "Vgroove" (**Figure 20b** and **c**). Indeed, with this type of wet etching the {111}-Si planes are revealed at the bottom of the trenches. This approach has the advantage to free the III-V layer from the APBs which doesn't form on Si(111) surface. The GaAs is then epitaxialy grown to obtain a nanoribbons array in the trenches. The growth process is achieved in a classical way with two steps: one low temperature nucleation (365°C) step followed by a fast growth at high temperature (570°C). The STEM images highlight some microtwins, at the Si/GaAs interface, which are trapped by the Vgroove structure (**Figure 20c**). However, outside that thin area the GaAs layer is single-domain with a good crystalline quality. The XRD rocking curve from the (004) peak was measured in both configuration parallel and perpendicular to the line. For a 200 nm-thick GaAs the FWHM of each peaks are measured at 400 arcsec and 550 arcsec for the perpendicular and parallel configuration respectively. That difference is attributed to the defects not trapped by the trenches in the parallel direction. Some of these defects can be seen on the STEM cross-section, parallel to the trench, of **Figure 20d**. The Moiré fringes are formed by the interferences between the Si et GaAs crystal at the V-groove level. Besides the defects trapping by the cavity, the low defectivity is ascribed to the stress relaxation by the partial dislocations associated to the stacking faults and microtwins at the interface. This phenomenon has already been reported with the InP growth in other works [60, 61].

surface of the GaAs as function of the trenches width. A remarkable achievement is the low TDD which decrease below 4.5�10<sup>5</sup> cm�<sup>2</sup> for the very narrow trenches of 80 nm (AR 3.75). Therefore such TDD is therefore very closed to the one of a bulk

*(a) GaAs nano-ridges in SAE. (b) TDD and PDD as function of the trench-width. From [62].*

*GaAs Compounds Heteroepitaxy on Silicon for Opto and Nano Electronic Applications*

*DOI: http://dx.doi.org/10.5772/intechopen.94609*

The planar defect density (essentially stacking faults) shows, however, an inverted relationship with the trench width. The PDD is indeed significantly higher in the narrow cavities. It rises from a value below 0.2 μm�<sup>1</sup> in the >300 nm-wide trenches to 0.5 μm�<sup>1</sup> for trenches below 100 nm-wide. The authors assume that the Shockley partial dislocation at the SF-planes ends may help to release the stress in the narrow

Furthermore, Baron et al. [63] highlighted the efficiency of the ART method for the optical emission of AlAs/InGaAs/AlAs QWs. The QWs are grown on top of a 150 nm-thick GaAs buffer layer in SiO2 trenches with differents aspect ratio ranging from 0.2 to 1.3 (**Figure 22a**). In this work a 1.3 AR is necessary to free the GaAs buffer layer from APBs and to obtain a PL at 300 K. This way the **Figure 22b** shows the normalized μPL spectra for InGaAs QWs with different Indium content. The PL peak position measurement combined with the InGaAs layer thickness measurement by STEM (**Figure 22c**) allows for the calculation of an Indium content of 7%,

16%, 35%, 42% in the 4 samples. These values are very close to the targeted concentrations. Besides, to observe the influence of defects at the local scale, CL

(**Figure 22d**). Since the layer is free of APBs, the dark zone, corresponding to nonluminescent areas, are attributed to the dislocations that are not trapped by the

This explanation of the TDs acting as luminescence quenchers was pushed further in another work [64] combining FIB-STEM, CL and strain measurement of the III-V nanoribbons by precession electron diffraction (PED) [65, 66]. The **Figure 23a**. shows a STEM cross-section of the nanoribbons with their AlAs/InGaAs QWs. The structural defects crossing the QWs are labeled from d1 to d5. Prior to the STEM lamella preparation CL intensity imaging (**Figure 23b**) was performed at the same location of the nanoribbon (the area is located thanks to platinum marker deposited on top of the NRs array). The authors highlighted that the luminescence is not homogenous along the NRs and the dark and bright area are bounded by two TDs indexed as d3 and d4 on the image. In addition, the CL peak position of the brighter area shift of about 10 nm toward the higher wavelength (**Figure 23c**). Both the intensity and the peak shifting can be spatially correlated to the 0.5% *ε*½ � <sup>110</sup> strain variation starting from the d3 dislocation and measured thanks to the PED method

measurements at 15 K were performed on top of the nanoribbon arrays

structure and propagating through the QWs.

). This result was observed on both GaAs and GaSb NRs.

GaAs substrate (�10<sup>5</sup> cm�<sup>2</sup>

trenches.

**Figure 21.**

(**Figure 23d**).

**147**

More recently, Kunert et al. [62] used a SAE approach to achieve some GaAs and GaSb nano-ridges (NRs) which come out from the cavities with tunable shapes and facets as function of the process conditions (**Figure 21a**). These type of NRs can serve as laser diodes structure as well as planar photodetectors. The nano-ridges growth is achieved in trenches where the silicon has been etched in wet solution to form a v-groove of Si-{111} planes. The defect density on the top surface of NRs was assessed in the direct space from electron channeling contrast imaging (ECCI). This latter method can be implemented more easily and with a better statistic than TEM. The graph of **Figure 21b** summarizes the TDD and planar defect density (PDD) in

#### **Figure 20.**

*(a) Principle of ART. (b) GaAs growth in V-groove shaped Si/SiO2 trenches. (c) SFs and microtwins at Si/ GaAs interface. (d) STEM cross-section along the trench. The TDs are indicated by the red arrows. The Moiré fringes are formed by the interferences between the Si et GaAs crystal at the V-groove level. From [58, 59].*

*GaAs Compounds Heteroepitaxy on Silicon for Opto and Nano Electronic Applications DOI: http://dx.doi.org/10.5772/intechopen.94609*

**Figure 21.** *(a) GaAs nano-ridges in SAE. (b) TDD and PDD as function of the trench-width. From [62].*

surface of the GaAs as function of the trenches width. A remarkable achievement is the low TDD which decrease below 4.5�10<sup>5</sup> cm�<sup>2</sup> for the very narrow trenches of 80 nm (AR 3.75). Therefore such TDD is therefore very closed to the one of a bulk GaAs substrate (�10<sup>5</sup> cm�<sup>2</sup> ). This result was observed on both GaAs and GaSb NRs. The planar defect density (essentially stacking faults) shows, however, an inverted relationship with the trench width. The PDD is indeed significantly higher in the narrow cavities. It rises from a value below 0.2 μm�<sup>1</sup> in the >300 nm-wide trenches to 0.5 μm�<sup>1</sup> for trenches below 100 nm-wide. The authors assume that the Shockley partial dislocation at the SF-planes ends may help to release the stress in the narrow trenches.

Furthermore, Baron et al. [63] highlighted the efficiency of the ART method for the optical emission of AlAs/InGaAs/AlAs QWs. The QWs are grown on top of a 150 nm-thick GaAs buffer layer in SiO2 trenches with differents aspect ratio ranging from 0.2 to 1.3 (**Figure 22a**). In this work a 1.3 AR is necessary to free the GaAs buffer layer from APBs and to obtain a PL at 300 K. This way the **Figure 22b** shows the normalized μPL spectra for InGaAs QWs with different Indium content. The PL peak position measurement combined with the InGaAs layer thickness measurement by STEM (**Figure 22c**) allows for the calculation of an Indium content of 7%, 16%, 35%, 42% in the 4 samples. These values are very close to the targeted concentrations. Besides, to observe the influence of defects at the local scale, CL measurements at 15 K were performed on top of the nanoribbon arrays (**Figure 22d**). Since the layer is free of APBs, the dark zone, corresponding to nonluminescent areas, are attributed to the dislocations that are not trapped by the structure and propagating through the QWs.

This explanation of the TDs acting as luminescence quenchers was pushed further in another work [64] combining FIB-STEM, CL and strain measurement of the III-V nanoribbons by precession electron diffraction (PED) [65, 66]. The **Figure 23a**. shows a STEM cross-section of the nanoribbons with their AlAs/InGaAs QWs. The structural defects crossing the QWs are labeled from d1 to d5. Prior to the STEM lamella preparation CL intensity imaging (**Figure 23b**) was performed at the same location of the nanoribbon (the area is located thanks to platinum marker deposited on top of the NRs array). The authors highlighted that the luminescence is not homogenous along the NRs and the dark and bright area are bounded by two TDs indexed as d3 and d4 on the image. In addition, the CL peak position of the brighter area shift of about 10 nm toward the higher wavelength (**Figure 23c**). Both the intensity and the peak shifting can be spatially correlated to the 0.5% *ε*½ � <sup>110</sup> strain variation starting from the d3 dislocation and measured thanks to the PED method (**Figure 23d**).

of the method. In fact, the TDs propagating through the dense {111}-planes can be blocked by the geometry of the patterns. In this case the aspect ratio (height on

fore, for example, with a 150-thick dielectric, the cavity must be no wider than �100 nm. Nevertheless, as we can see on the figure, the planar defects which lie

width oxide trenches on Si(001) etched by a wet solution of KOH to form a "Vgroove" (**Figure 20b** and **c**). Indeed, with this type of wet etching the {111}-Si planes are revealed at the bottom of the trenches. This approach has the advantage to free the III-V layer from the APBs which doesn't form on Si(111) surface. The GaAs is then epitaxialy grown to obtain a nanoribbons array in the trenches. The growth process is achieved in a classical way with two steps: one low temperature nucleation (365°C) step followed by a fast growth at high temperature (570°C). The STEM images highlight some microtwins, at the Si/GaAs interface, which are trapped by the Vgroove structure (**Figure 20c**). However, outside that thin area the GaAs layer is single-domain with a good crystalline quality. The XRD rocking curve from the (004) peak was measured in both configuration parallel and perpendicular to the line. For a 200 nm-thick GaAs the FWHM of each peaks are measured at 400 arcsec and 550 arcsec for the perpendicular and parallel configuration respectively. That difference is attributed to the defects not trapped by the trenches in the parallel direction. Some of these defects can be seen on the STEM cross-section, parallel to the trench, of **Figure 20d**. The Moiré fringes are formed by the interferences between the Si et GaAs crystal at the V-groove level. Besides the defects trapping by the cavity, the low defectivity is ascribed to the stress relaxation by the partial dislocations associated to the stacking faults and microtwins at the interface. This phenomenon has already

parallel to the trenches can be more difficult (or impossible) to trap.

*=*

In the example of ART from the works of Lau et al. [58], they use about 100 nm-

More recently, Kunert et al. [62] used a SAE approach to achieve some GaAs and GaSb nano-ridges (NRs) which come out from the cavities with tunable shapes and facets as function of the process conditions (**Figure 21a**). These type of NRs can serve as laser diodes structure as well as planar photodetectors. The nano-ridges growth is achieved in trenches where the silicon has been etched in wet solution to form a v-groove of Si-{111} planes. The defect density on the top surface of NRs was assessed in the direct space from electron channeling contrast imaging (ECCI). This latter method can be implemented more easily and with a better statistic than TEM. The graph of **Figure 21b** summarizes the TDD and planar defect density (PDD) in

*(a) Principle of ART. (b) GaAs growth in V-groove shaped Si/SiO2 trenches. (c) SFs and microtwins at Si/ GaAs interface. (d) STEM cross-section along the trench. The TDs are indicated by the red arrows. The Moiré fringes are formed by the interferences between the Si et GaAs crystal at the V-groove level. From [58, 59].*

*<sup>l</sup>*≥ *tan θ*ð Þ <sup>111</sup> ¼ tan 54 ð Þ¼ *:*7° 1*:*4. There-

) of the pattern must be such that *h*

been reported with the InP growth in other works [60, 61].

width *h=l*

*Post-Transition Metals*

**Figure 20.**

**146**

**3. Part 3: realization of InAs QDs/GaAs laser emitter on APB-free**

*GaAs Compounds Heteroepitaxy on Silicon for Opto and Nano Electronic Applications*

The advantages of high data rate, broad bandwidth, mature fabrication processes and low power consumption make Si photonics become a desirable approach, meeting the future demands of optical interconnections. To date, significant achievements have been made in Si photonics and most of key components have been well demonstrated, including low-loss waveguides, high-speed modulators and high-performance photodetectors [70–74]. However, the realization of highperformance Si-based on-chip light sources still remains challenging for the full integration of optoelectronics integrated circuits [75]. Among various of approaches, monolithically integrating high-performance III-V QD lasers on Si substrate has been considered as a promising method to develop an on-chip optical source for Si photonics [76–78]. The advanced properties of low threshold, high defects tolerance and high temperature stability contribute largely to the develop-

Before illustrating the recent progress of QD lasers grown on Si (001) substrates,

, QW lasers directly grown on Si still suffered on their high threshold and

it is worth to discuss briefly about some key milestones in the development of monolithic integration of III-V lasers on Si. Although some optimized heteroepitaxy techniques have reduced the TDD of III-V on Si from originally <sup>10</sup><sup>9</sup> cm<sup>2</sup> to

limited lifetime due to the enhanced TD generation [82–85]. An early result presented a QW laser with InP buffer as thick as 15 μm with decent performance and lifetime [86]. However, due to the difference of thermal expansion coefficient between III-V epi-layer and Si substrate, the thick buffer is also vulnerable to the formation of micro-cracks, which destroys the yield of Si-based devices [87]. The research of III-V QD lasers on Si (001) comes out since early 2000s. After the early attempt by using droplet epitaxy to grow QD lasers, the successful address of Stranski-Krastanov growth mode on the growth of QDs presents significant advantages on emitting light with the presence of high TDD caused by mismatch in lattice constants and thermal expansion coefficients [88, 89]. By taking the benefits of ultra-high vacuum and precise control, MBE system has been widely considered as a

Recently, numerous achievements that pursuing high performance III-V QD lasers on Si have been demonstrated. The offcut Si substrate was addressed initially to prevent the formation of APB. In 2001, the first QD laser on Si emitting at 855 nm at room temperature under continuous-wave operation was presented by growing InGaAs QDs on Si substrate with MOCVD [90]. More importantly, the aging test illustrated the advantage of reliability for QD lasers on Si compared with QW counterparts. By further optimizing the active region and III-V buffer, such as utilizing DFLs and P-type modulation doped QD region, the performance of QD lasers on Si was highly improved, realizing a characteristic temperature (T0) of 244 K between operation temperature of 25–95°C and a reduced threshold current density of 900A/cm<sup>2</sup> at that time [48, 91]. These results suggest the possibility of QD lasers directly grown on Si substrate as an efficient and reliable light source for

The aforementioned works of QD lasers were all operated under emission of 1.1 μm. However, the recent ever-growing demands on telecommunication and data-communication system, led to significant achievements on 1.3 μm InAs/GaAs QD lasers on Si substrate. The first room temperature 1.3 μm emission of QDs on Si grown by MOCVD was achieved by Li et al. at 2008, with the help of Sb [92].

suitable technique for the growth of high-performance QDs.

**GaAs/Si platform**

ment of QD lasers [27, 79–81].

<sup>10</sup><sup>6</sup> cm<sup>2</sup>

Si photonics.

**149**

**3.1 The Development of QD laser on Si**

*DOI: http://dx.doi.org/10.5772/intechopen.94609*

#### **Figure 22.**

*(a) low magnification cross-sectional STEM image of a GaAs layer grown in 140 nm wide SiO2 trenches on (001)-oriented Si substrate showing a good uniformity of the selective growth. The trenches are oriented along the [1–10] direction and are 180 nm deep. (b) Normalized room temperature lPL spectra of different InGaAs. QWs having different composition of Indium of (#1) 10%, (#2) 20%, (#3) 30%, and (#4) 40%. (c) Crosssectional TEM image of the top layers showing the stack of GaAs/AlAs/InGaAs/AlAs/GaAs layers with no crystalline defects. (d) 5 K panchromatic CL mapping of the nanoribbons array. From [64].*

#### **Figure 23.**

*Spatial correlation between mappings: (a) cross section STEM, (b) top-view CL intensity, (c) CL peak positions, and (d) cross section ε [110], ε[001], and ε [110, 001] strain distortions realized on a single III-V QWF. The high luminescent area is bounded by dislocations d3 and d4 and associated with a peak position shift toward higher wavelength. ε [110] shows a 0.5% distortion along this III-V QWF, and no significant distortion for ε[001] and ε [110, 001]. From [64].*

The SAE approach entails a large number of variants, including epitaxial lateral overgrowth ELO [67] and confined epitaxial lateral overgrowth (CELO) [68]. These alternatives often use a "3D" confinement of defects. However, if they are in certain cases, very efficient, they generally require a complex and cost consuming patterning of the substrates. For an overview of the latter methods one can refer to the references [59, 69].

#### **2.4 Summary**

**In the past 30 years, efforts have been made to decrease the TDs induced by the lattice mismatch between GaAs and Si. Introduction of DFL method as well as the use of Aspect Ratio trapping method allow to decrease the threading dislocation density in the 105 –106 cm**�**<sup>2</sup> range, value required to obtain efficient devices.**
