**3. Results and discussion**

### **3.1 DC performances of NWFETs and NSFETs**

**Figure 3** shows the *Ids* of all the GAAFETs having different WNW or WNS at the fixed Nch of 3 at the drain voltages (*Vds*) of 0.70 V. It is not shown in this figure, but the *Ids* increases generally as the WNW or WNS increases irrespective of Nch. As the WNW increases, the *Ids* shifts leftward and the gate-induced drain leakage (GIDL) increases by losing the gate-to-channel controllability [27]. P-type NWFETs have larger GIDL than n-type NWFETs due to larger S/D doping penetrations into the channel for p-type devices. On the other hand, NSFETs have small GIDL and *Ids* shifts as thin TNS of 5 nm forms 1-D structural confinement and maintains good short channel characteristics. To the following, there are three applications at different off-state currents (*Ioff*): LP at the *Ioff* of 100 pA/μm, SP at the *Ioff* of 10 nA/μm, and HP at the *Ioff* of 100 nA/μm [28]. These values were normalized to NP.

**Figure 4** shows SS and DIBL of all the devices. Threshold voltages (*Vth*) and SS are extracted at the constant current of Weff/Lg × 108 A, where Weff is the effective width equal to 2 × Hfin + Wfin for FinFETs, 4 × WNW × Nch for NWFETs, and (2 × WNS + 2 × TNS) × Nch for NSFETs. DIBL is calculated as the difference of the *Vth* at two different *Vds* of 0.05 and 0.70 V for n-type (−0.05 and − 0.70 V for p-type) devices [29]. NWFETs degrade the short channel characteristics much than FinFETs as the WNW is 9 and 10 nm. NSFETs, on the other hand, have smaller SS and DIBL than FinFETs even as the WNS increases up to 50 nm because the gate-to-channel controllability is maintained by GAA structure and thin TNS of 5 nm. But when the NWFETs have ultra-small WNS of 5 or 6 nm, 2-D structural confinement decreases the SS and DIBL greatly, which would be preferable for LP applications. It is not shown in this figure, but the SS and DIBL are independent of Nch.

**Figure 5** summarizes the effective currents (*Ieff*) of n-type (top) and p-type (bottom) GAAFETs having different WNW (or WNS) and Nch. *Ieff* was calculated using two *Ids* at different *Vds* and gate voltages (*Vgs*) as

$$I\_{\rm eff} = \left(I\_H - I\_L\right) / \ln\left(\frac{I\_H}{I\_L}\right) \tag{1}$$

**161**

**Figure 4.**

**Figure 3.**

*Gate-All-Around FETs: Nanowire and Nanosheet Structure*

where *IH* = *Ids* (*Vgs* = *VDD*, *Vds* = *VDD*/2) and *IL* = *Ids* (*Vgs* = *VDD*/2, *Vds* = *VDD*) [30], and *VDD* is the operation voltage fixed to 0.7 V. All the *Ieff* were normalized to the NP, and the *Ioff* were fixed to 10 nA/μm for SP applications. GAAFETs need to have at least the Nch of 3 to outperform the FinFETs. As the WNW is 9 nm, both n-type and p-type NWFETs suffer from short channel effects (SCEs) and thus have smaller *Ieff* than the devices having smaller WNW in spite of larger Weff. NSFETs, on the other hand, have larger *Ieff* as the WNS is larger as the SCEs are reduced by thin TNS of 5 nm. But even though small same SS and DIBL are maintained for all the Nch, the

*SS (left) and DIBL (right) of FinFETs, NWFETs, and NSFETs having fixed Nch of 3. It is not shown in this* 

*Ids of n-type (top) and p-type (bottom) NWFETs and NSFETs having different WNW or WNS at the fixed Nch of 3 at the drain voltages (Vds) of 0.70 V. it is not shown in this figure, but the GAAFETs have the same Ids*

**Figure 6** shows the S/D parasitic resistance (*Rsd*) of the GAAFETs having the WNW or 7 nm and the WNS of 30 nm as a function of Nch. Other WNW and WNS have the same *Rsd* trends and thus are not shown in this work. *Rsd* was possibly extracted using *Y*-function method due to the linearity of *Y*-function at high *Vgs* [31]. As the

increasing rate of *Ieff* as a function of Nch decreases as Nch increases.

*figure, but the GAAFETs have the same SS and DIBL irrespective of Nch.*

*trends irrespective of Nch (Ids increases as the WNW or WNS increases).*

*DOI: http://dx.doi.org/10.5772/intechopen.94060*

*Gate-All-Around FETs: Nanowire and Nanosheet Structure DOI: http://dx.doi.org/10.5772/intechopen.94060*

**Figure 3.**

*Nanowires - Recent Progress*

**3. Results and discussion**

**Figure 2.**

normalized to NP.

**3.1 DC performances of NWFETs and NSFETs**

SS are extracted at the constant current of Weff/Lg × 108

shown in this figure, but the SS and DIBL are independent of Nch.

using two *Ids* at different *Vds* and gate voltages (*Vgs*) as

**Figure 3** shows the *Ids* of all the GAAFETs having different WNW or WNS at the fixed Nch of 3 at the drain voltages (*Vds*) of 0.70 V. It is not shown in this figure, but the *Ids* increases generally as the WNW or WNS increases irrespective of Nch. As the WNW increases, the *Ids* shifts leftward and the gate-induced drain leakage (GIDL) increases by losing the gate-to-channel controllability [27]. P-type NWFETs have larger GIDL than n-type NWFETs due to larger S/D doping

*Process flows of GAAFETs. Key process schemes of GAAFETs are Si0.7Ge0.3/Si multi-layer stacking,* 

*inner-spacer formation, and channel release by etching Si0.7Ge0.3 regions selectively.*

penetrations into the channel for p-type devices. On the other hand, NSFETs have small GIDL and *Ids* shifts as thin TNS of 5 nm forms 1-D structural confinement and maintains good short channel characteristics. To the following, there are three applications at different off-state currents (*Ioff*): LP at the *Ioff* of 100 pA/μm, SP at the *Ioff* of 10 nA/μm, and HP at the *Ioff* of 100 nA/μm [28]. These values were

**Figure 4** shows SS and DIBL of all the devices. Threshold voltages (*Vth*) and

tive width equal to 2 × Hfin + Wfin for FinFETs, 4 × WNW × Nch for NWFETs, and (2 × WNS + 2 × TNS) × Nch for NSFETs. DIBL is calculated as the difference of the *Vth* at two different *Vds* of 0.05 and 0.70 V for n-type (−0.05 and − 0.70 V for p-type) devices [29]. NWFETs degrade the short channel characteristics much than FinFETs as the WNW is 9 and 10 nm. NSFETs, on the other hand, have smaller SS and DIBL than FinFETs even as the WNS increases up to 50 nm because the gate-to-channel controllability is maintained by GAA structure and thin TNS of 5 nm. But when the NWFETs have ultra-small WNS of 5 or 6 nm, 2-D structural confinement decreases the SS and DIBL greatly, which would be preferable for LP applications. It is not

**Figure 5** summarizes the effective currents (*Ieff*) of n-type (top) and p-type (bottom) GAAFETs having different WNW (or WNS) and Nch. *Ieff* was calculated

( )/ ln *<sup>H</sup>*

= −

*<sup>I</sup> I II*

*L*

*I*

*eff H L*

A, where Weff is the effec-

(1)

**160**

*Ids of n-type (top) and p-type (bottom) NWFETs and NSFETs having different WNW or WNS at the fixed Nch of 3 at the drain voltages (Vds) of 0.70 V. it is not shown in this figure, but the GAAFETs have the same Ids trends irrespective of Nch (Ids increases as the WNW or WNS increases).*

#### **Figure 4.**

*SS (left) and DIBL (right) of FinFETs, NWFETs, and NSFETs having fixed Nch of 3. It is not shown in this figure, but the GAAFETs have the same SS and DIBL irrespective of Nch.*

where *IH* = *Ids* (*Vgs* = *VDD*, *Vds* = *VDD*/2) and *IL* = *Ids* (*Vgs* = *VDD*/2, *Vds* = *VDD*) [30], and *VDD* is the operation voltage fixed to 0.7 V. All the *Ieff* were normalized to the NP, and the *Ioff* were fixed to 10 nA/μm for SP applications. GAAFETs need to have at least the Nch of 3 to outperform the FinFETs. As the WNW is 9 nm, both n-type and p-type NWFETs suffer from short channel effects (SCEs) and thus have smaller *Ieff* than the devices having smaller WNW in spite of larger Weff. NSFETs, on the other hand, have larger *Ieff* as the WNS is larger as the SCEs are reduced by thin TNS of 5 nm. But even though small same SS and DIBL are maintained for all the Nch, the increasing rate of *Ieff* as a function of Nch decreases as Nch increases.

**Figure 6** shows the S/D parasitic resistance (*Rsd*) of the GAAFETs having the WNW or 7 nm and the WNS of 30 nm as a function of Nch. Other WNW and WNS have the same *Rsd* trends and thus are not shown in this work. *Rsd* was possibly extracted using *Y*-function method due to the linearity of *Y*-function at high *Vgs* [31]. As the

**Figure 5.**

*Ieff of n-type (top) and p-type (bottom) GAAFETs having different WNW (or WNS) and Nch. Ieff of n-type and p-type FinFETs are also specified as yellow symbols. Blue regions indicate that the GAAFETs have superior Ieff than the FinFETs.*

#### **Figure 6.**

*Rsd of n-type and p-type GAAFETs having the WNW of 7 nm and the WNS of 30 nm as a function of Nch (left) and the 2-D schematic diagram of half of the GAAFETs showing the current paths and Rsd components (right).*

Nch increases, *Rsd* of the GAAFETs decrease but at decreasing rate. Furthermore, *Rsd* becomes saturated as the Nch is 3 or 4. This phenomena can be explained by 2-D schematic diagrams shown in the right of **Figure 6**. Since the S/D contacts reside at the top of the S/D epi, current paths start from the top toward the channels at the bottom. As the Nch increases, longer current paths are needed to flow the bottomside channels, facing more *Rsd* components at the S/D epi. Thus, increasing the Nch beyond 3 or 4 does not help DC performance improvements greatly.

### **3.2 AC performances of NWFETs and NSFETs**

**Figure 7** summarizes the gate capacitances (*Cgg*) of all the GAAFETs. The *Cgg* is extracted at the *Vgs* and the *Vds* of *VDD*. Generally, *Cgg* increases as the WNW (or WNS) or Nch increases due to the increased Weff. PFETs have larger *Cgg* than NFETs due to larger S/D doping concentrations and penetrations into the channels. Different

**163**

**Figure 8.**

**Figure 7.**

*Cgg than the FinFETs.*

delay (= *IeffVDD*/*Cgg*) as the Nch increases.

from the *Ieff* trends, the GAAFETs have Nch smaller than 3 to outperform the FinFETs, thus there are performance trade-offs between *Ieff* and *Cgg* as a function of Nch. Furthermore, the increasing rate of *Cgg* as a function of Nch is constant while the increasing rate of *Ieff* as a function of Nch decreases, which would degrade the RC

*Cgg and Cpara of NWFETs (left) and NSFETs (right) having different WNW (or WNS) at the fixed Nch of 3 and having different Nch at the fixed WNW of 7 nm (or WNS of 30 nm). Percentages represent the Cpara/Cgg.*

*Cgg of n-type (top) and p-type (bottom) GAAFETs having different WNW (or WNS) and Nch. Cgg of n-type and p-type FinFETs are also specified as yellow symbols. Blue regions indicate that the GAAFETs have smaller* 

*Gate-All-Around FETs: Nanowire and Nanosheet Structure*

*DOI: http://dx.doi.org/10.5772/intechopen.94060*

*Gate-All-Around FETs: Nanowire and Nanosheet Structure DOI: http://dx.doi.org/10.5772/intechopen.94060*

#### **Figure 7.**

*Nanowires - Recent Progress*

**Figure 5.**

**Figure 6.**

*than the FinFETs.*

**162**

Nch increases, *Rsd* of the GAAFETs decrease but at decreasing rate. Furthermore, *Rsd* becomes saturated as the Nch is 3 or 4. This phenomena can be explained by 2-D schematic diagrams shown in the right of **Figure 6**. Since the S/D contacts reside at the top of the S/D epi, current paths start from the top toward the channels at the bottom. As the Nch increases, longer current paths are needed to flow the bottomside channels, facing more *Rsd* components at the S/D epi. Thus, increasing the Nch

*Rsd of n-type and p-type GAAFETs having the WNW of 7 nm and the WNS of 30 nm as a function of Nch (left) and the 2-D schematic diagram of half of the GAAFETs showing the current paths and Rsd components (right).*

*Ieff of n-type (top) and p-type (bottom) GAAFETs having different WNW (or WNS) and Nch. Ieff of n-type and p-type FinFETs are also specified as yellow symbols. Blue regions indicate that the GAAFETs have superior Ieff*

**Figure 7** summarizes the gate capacitances (*Cgg*) of all the GAAFETs. The *Cgg* is extracted at the *Vgs* and the *Vds* of *VDD*. Generally, *Cgg* increases as the WNW (or WNS) or Nch increases due to the increased Weff. PFETs have larger *Cgg* than NFETs due to larger S/D doping concentrations and penetrations into the channels. Different

beyond 3 or 4 does not help DC performance improvements greatly.

**3.2 AC performances of NWFETs and NSFETs**

*Cgg of n-type (top) and p-type (bottom) GAAFETs having different WNW (or WNS) and Nch. Cgg of n-type and p-type FinFETs are also specified as yellow symbols. Blue regions indicate that the GAAFETs have smaller Cgg than the FinFETs.*

#### **Figure 8.**

*Cgg and Cpara of NWFETs (left) and NSFETs (right) having different WNW (or WNS) at the fixed Nch of 3 and having different Nch at the fixed WNW of 7 nm (or WNS of 30 nm). Percentages represent the Cpara/Cgg.*

from the *Ieff* trends, the GAAFETs have Nch smaller than 3 to outperform the FinFETs, thus there are performance trade-offs between *Ieff* and *Cgg* as a function of Nch. Furthermore, the increasing rate of *Cgg* as a function of Nch is constant while the increasing rate of *Ieff* as a function of Nch decreases, which would degrade the RC delay (= *IeffVDD*/*Cgg*) as the Nch increases.

**Figure 8** shows the *Cgg* and parasitic capacitances (*Cpara*) of the GAAFETs varying Nch and WNW (or WNS). *Cpara* is extracted at off-state for SP applications. For all the cases, PFETs have larger *Cpara* than NFETs due to larger S/D doping and penetrations into the channels [20]. At the fixed Nch of 3, larger WNW or WNS, except for p-type NWFETs, decreases the *Cpara*/*Cgg* because the proportion of the channels out of the metal gate increases. For the same reason, larger Nch decreases the *Cpara*/*Cgg*. Large *Cpara*/*Cgg* at the WNW of 9 nm for NFETs is because large SS forms on state before reaching strong inversion region.

**Figure 9** shows the S/D doping profiles of NFETs (top) and PFETs (bottom) having different WNW at the fixed Nch of 3. In general, NFETs have larger doping concentrations in the middle of channels than PFETs because the Ge intermixing within multi-stacked Si/Si0.7Ge0.3 layers increases the Ge concentration at the channels and assists more phosphorus dopants diffusing into the channels while it segregates boron dopants [32–34]. Both NFETs and PFETs increase the doping concentrations in the middle of channels as the WNW increases because the dopant segregations near the low-k spacer regions decrease [35]. But PFETs increase the doping concentrations in the middle of channels much due to smaller Ge intermixing for larger WNW. This great increase of the doping concentrations in the middle of channels increases the *Cpara*/*Cgg* for p-type NWFETs (as shown in **Figure 8**).

**Figure 10** finalizes the RC delay of all the GAAFETs for LP, SP, and HP applications. N-type FinFETs have smaller RC delay than p-type FinFETs for all the applications due to better short channel characteristics, greater *Ieff* (as shown in **Figure 5**) and smaller *Cgg* (as shown in **Figure 8**). For LP applications, n-type GAAFETs having

**Figure 9.**

*S/D doping profiles of NFETs (top) and PFETs (bottom) having different WNW at the fixed Nch of 3. Doping concentrations in the middle of top-side channels are also specified.*

**165**

**4. Conclusion**

**Figure 10.**

*Gate-All-Around FETs: Nanowire and Nanosheet Structure*

small WNW equal to 5 or 6 nm can outperform n-type FinFETs by decreasing SS and DIBL critically. But as the Nch is 1 (or 5), the *Ieff* decreases greatly (or the *Cgg* increases greatly), thus degrading the RC delay. On the other hand, p-type GAAFETs have more WNW or WNS options to outperform p-type FinFETs because boron dopants of the GAAFETs are segregated by Si/Si0.7Ge0.3 intermixing and have more abrupt S/D doping profile than p-type FinFETs. For LP applications, both n- and p-type GAAFETs have the minimum RC delay at the WNW of 5 nm and the Nch of 4. For both SP and HP applications, both n- and p-type GAAFETs have the minimum RC delay at the WNS of 50 nm and the Nch of 3. As the WNS increases beyond 50 nm, RC delay decrease but a little (as shown in **Appendix**). All these RC delay are achieved by enhancing the *Ieff* rather than the *Cgg*. To outperform the FinFETs, therefore, GAAFETs should be NWFETs, showing outstanding short channel characteristics, for LP applications and

*RC delay of all the GAAFETs for (a) LP, (b) SP, and (c) HP applications. RC delay of FinFETs for three different applications are also specified. The devices having the RC delay smaller than FinFETs are marked as yellow.*

NSFETs, showing superior DC performance, for SP and HP applications.

3-nm-node GAAFETs have been analyzed by changing WNW (or WNS) and Nch using fully-calibrated TCAD. Compared to FinFETs, GAAFETs have smaller and

*DOI: http://dx.doi.org/10.5772/intechopen.94060*

*Gate-All-Around FETs: Nanowire and Nanosheet Structure DOI: http://dx.doi.org/10.5772/intechopen.94060*

**Figure 10.**

*Nanowires - Recent Progress*

before reaching strong inversion region.

**Figure 8** shows the *Cgg* and parasitic capacitances (*Cpara*) of the GAAFETs varying Nch and WNW (or WNS). *Cpara* is extracted at off-state for SP applications. For all the cases, PFETs have larger *Cpara* than NFETs due to larger S/D doping and penetrations into the channels [20]. At the fixed Nch of 3, larger WNW or WNS, except for p-type NWFETs, decreases the *Cpara*/*Cgg* because the proportion of the channels out of the metal gate increases. For the same reason, larger Nch decreases the *Cpara*/*Cgg*. Large *Cpara*/*Cgg* at the WNW of 9 nm for NFETs is because large SS forms on state

**Figure 9** shows the S/D doping profiles of NFETs (top) and PFETs (bottom) having different WNW at the fixed Nch of 3. In general, NFETs have larger doping concentrations in the middle of channels than PFETs because the Ge intermixing within multi-stacked Si/Si0.7Ge0.3 layers increases the Ge concentration at the channels and assists more phosphorus dopants diffusing into the channels while it segregates boron dopants [32–34]. Both NFETs and PFETs increase the doping concentrations in the middle of channels as the WNW increases because the dopant segregations near the low-k spacer regions decrease [35]. But PFETs increase the doping concentrations in the middle of channels much due to smaller Ge intermixing for larger WNW. This great increase of the doping concentrations in the middle of channels

**Figure 10** finalizes the RC delay of all the GAAFETs for LP, SP, and HP applications. N-type FinFETs have smaller RC delay than p-type FinFETs for all the applications due to better short channel characteristics, greater *Ieff* (as shown in **Figure 5**) and smaller *Cgg* (as shown in **Figure 8**). For LP applications, n-type GAAFETs having

*S/D doping profiles of NFETs (top) and PFETs (bottom) having different WNW at the fixed Nch of 3. Doping* 

*concentrations in the middle of top-side channels are also specified.*

increases the *Cpara*/*Cgg* for p-type NWFETs (as shown in **Figure 8**).

**164**

**Figure 9.**

*RC delay of all the GAAFETs for (a) LP, (b) SP, and (c) HP applications. RC delay of FinFETs for three different applications are also specified. The devices having the RC delay smaller than FinFETs are marked as yellow.*

small WNW equal to 5 or 6 nm can outperform n-type FinFETs by decreasing SS and DIBL critically. But as the Nch is 1 (or 5), the *Ieff* decreases greatly (or the *Cgg* increases greatly), thus degrading the RC delay. On the other hand, p-type GAAFETs have more WNW or WNS options to outperform p-type FinFETs because boron dopants of the GAAFETs are segregated by Si/Si0.7Ge0.3 intermixing and have more abrupt S/D doping profile than p-type FinFETs. For LP applications, both n- and p-type GAAFETs have the minimum RC delay at the WNW of 5 nm and the Nch of 4. For both SP and HP applications, both n- and p-type GAAFETs have the minimum RC delay at the WNS of 50 nm and the Nch of 3. As the WNS increases beyond 50 nm, RC delay decrease but a little (as shown in **Appendix**). All these RC delay are achieved by enhancing the *Ieff* rather than the *Cgg*. To outperform the FinFETs, therefore, GAAFETs should be NWFETs, showing outstanding short channel characteristics, for LP applications and NSFETs, showing superior DC performance, for SP and HP applications.

#### **4. Conclusion**

3-nm-node GAAFETs have been analyzed by changing WNW (or WNS) and Nch using fully-calibrated TCAD. Compared to FinFETs, GAAFETs have smaller and

SS and DIBL as the WNW is smaller than 9 nm but irrespective of the WNS. Both *Ieff* and *Cgg* of the GAAFETs increase as the Nch increases, but the increasing rate of *Ieff* decreases due to the increase of *Rsd* at the longer S/D epi. The increasing rate of *Cgg*, on the other hand, is almost constant. Because of these phenomena, Minimum RC delay are formed at the middle Nch of 3 or 4. The NWFETs having the WNW of 5 or 6 nm achieve smaller RC delay than the FinFETs by achieving better gate electronics for LP applications, whereas the NSFETs having the WNS of 40 or 50 nm increase the *Ieff* greatly and thus decrease the RC delay for SP and HP applications. Overall, GAAFETs are possible candidates to substitute FinFETs in the 3-nm technology node for all the applications by adopting different WNW or WNS.
