Gate-All-Around FETs: Nanowire and Nanosheet Structure

*Jun-Sik Yoon, Jinsu Jeong, Seunghwan Lee, Junjong Lee and Rock-Hyun Baek*

### **Abstract**

DC/AC performances of 3-nm-node gate-all-around (GAA) FETs having different widths and the number of channels (Nch) from 1 to 5 were investigated thoroughly using fully-calibrated TCAD. There are two types of GAAFETs: nanowire (NW) FETs having the same width (WNW) and thickness of the channels, and nanosheet (NS) FETs having wide width (WNS) but the fixed thickness of the channels as 5 nm. Compared to FinFETs, GAAFETs can maintain good short channel characteristics as the WNW is smaller than 9 nm but irrespective of the WNS. DC performances of the GAAFETs improve as the Nch increases but at decreasing rate because of the parasitic resistances at the source/drain epi. On the other hand, gate capacitances of the GAAFETs increase constantly as the Nch increases. Therefore, the GAAFETs have minimum RC delay at the Nch near 3. For low power applications, NWFETs outperform FinFETs and NSFETs due to their excellent short channel characteristics by 2-D structural confinement. For standard and high performance applications, NSFETs outperform FinFETs and NWFETs by showing superior DC performances arising from larger effective widths per footprint. Overall, GAAFETs are great candidates to substitute FinFETs in the 3-nm technology node for all the applications.

**Keywords:** gate-all-around, nanowire, nanosheet, field-effect transistors, fin, RC delay, parasitic resistance, parasitic capacitance

#### **1. Introduction**

Gate-all-around (GAA) is a widely-using structure such as logic field-effect transistor (FET) due to its excellent short channel characteristics [1–6] or its high surface-to-volume ratio [7, 8], 3-D NAND flash memory for bit-cost scalability [9, 10], photodiode due to its waveguide effect [11, 12], and gas sensor due to its high physical fill factor or surface-to-volume ratio [13, 14]. Especially for logic applications, GAAFETs have been introduced by attaining good gate electronics and increasing current drivability under the same active area.

Currently, fin-shaped FETs (FinFETs) have been scaled down to 10-nm node [15] and further to 5-nm node [16] by forming ultra-sharp fin for high current drivability while maintaining gate-to-channel controllability. GAAFETs are possibly showing great potential to substitute FinFETs in the following technology node, and the performance comparisons between FinFETs and GAAFETs have been investigated [3–6, 17]. But more detailed analysis between FinFETs and GAAFETs

is needed to set the device guideline by considering fine TCAD calibration and middle-of-line levels.

Therefore, in this work, DC/AC performances of 3-nm-node GAAFETs were investigated using fully-calibrated TCAD platform. By changing the GAA geometries, we found optimal GAA structure to minimize the RC delay for three different applications such as low power (LP), standard performance (SP), and high performance (HP) applications.
