**Appendices and nomenclature**

**Figure A1.**

*Ieff, Cgg, and RC delay of the NSFETs having the WNS of 40, 50, 60, 70, 80, 90, and 100 nm at the fixed Nch of 3 for SP and HP applications.*

**Figure A1** shows the DC/AC performances of the NSFETs as the WNS increases from 40 to 100 nm. Minimum RC delay are formed at the WNS of 50 nm and the Nch of 3 as shown in **Figure 10**, but much smaller RC delay can be attained as the WNS increases to 100 nm by increasing the *Ieff* rather than the *Cgg* even though larger WNS extends the device area. For the most, RC delay decrease by 5.4% for PFETs as the WNS increases from 40 to 100 nm.

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**Author details**

Republic of Korea

Jun-Sik Yoon, Jinsu Jeong, Seunghwan Lee, Junjong Lee and Rock-Hyun Baek\* Electrical Engineering, Pohang University of Science and Technology, Pohang,

© 2020 The Author(s). Licensee IntechOpen. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/ by/3.0), which permits unrestricted use, distribution, and reproduction in any medium,

\*Address all correspondence to: rh.baek@postech.ac.kr

provided the original work is properly cited.

*Gate-All-Around FETs: Nanowire and Nanosheet Structure*

*DOI: http://dx.doi.org/10.5772/intechopen.94060*

*Gate-All-Around FETs: Nanowire and Nanosheet Structure DOI: http://dx.doi.org/10.5772/intechopen.94060*

*Nanowires - Recent Progress*

**Conflict of interest**

SS and DIBL as the WNW is smaller than 9 nm but irrespective of the WNS. Both *Ieff* and *Cgg* of the GAAFETs increase as the Nch increases, but the increasing rate of *Ieff* decreases due to the increase of *Rsd* at the longer S/D epi. The increasing rate of *Cgg*, on the other hand, is almost constant. Because of these phenomena, Minimum RC delay are formed at the middle Nch of 3 or 4. The NWFETs having the WNW of 5 or 6 nm achieve smaller RC delay than the FinFETs by achieving better gate electronics for LP applications, whereas the NSFETs having the WNS of 40 or 50 nm increase the *Ieff* greatly and thus decrease the RC delay for SP and HP applications. Overall, GAAFETs are possible candidates to substitute FinFETs in the 3-nm technology

**Figure A1** shows the DC/AC performances of the NSFETs as the WNS increases from 40 to 100 nm. Minimum RC delay are formed at the WNS of 50 nm and the Nch of 3 as shown in **Figure 10**, but much smaller RC delay can be attained as the WNS increases to 100 nm by increasing the *Ieff* rather than the *Cgg* even though larger WNS extends the device area. For the most, RC delay decrease by 5.4% for PFETs as the

*Ieff, Cgg, and RC delay of the NSFETs having the WNS of 40, 50, 60, 70, 80, 90, and 100 nm at the fixed Nch of 3* 

node for all the applications by adopting different WNW or WNS.

The authors declare no conflict of interests.

**Appendices and nomenclature**

WNS increases from 40 to 100 nm.

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**Figure A1.**

*for SP and HP applications.*
