**1. Introduction**

Recently much interest has been developed to control the band gap as a function of diameter of Si nanowires (Si NWs) to exploit the quantum size effect for photovoltaic applications [1–5], and its extension according to Moore's law in view of the ongoing downscaling of integrated circuits (ICs) technologies as well as nano devices. Specially Si NWs are remarkably important for the fabrication of nanoscale devices such as transistors [6], sensors [7, 8], and thermoelectric devices [9]. Vapor–liquid–solid (VLS) mechanism provides a unique opportunity to investigate the crystalline quality and structures of single NW, where density, orientation, and periodicity of Si NWs system can be influenced by growth parameters such as

temperature, pressure, plasma treatment, dopants [10–12], and the type of catalyst [13, 14], surface condition of substrate as well as size [15] of the metal Nanodroplets (NDs), shown in **Figure 1**. Si NWs growth by VLS mode using various material catalysts, such as Au, Al, Ga, In, Pb, Sn and Zn have been reported [16–25].

Many researchers already grown vertically aligned Si NWs using Au-catalyst, which is not useful candidate for the application of nanoscale devices including solar cell and LEDs because it creates deep acceptor energy level at 0.54 eV in the Si band gap, whereas In-catalyst creates shallow accepter energy level at 0.16 eV in the Si band gap. Au-catalyst particles are strongly degrading the minority carrier life time, while In-catalyst particles are boosting to the carrier life time [26]. Previously, randomly oriented Si NWs were grown by Jeon and Kamisako *et al.* using different type of catalysts including In-metal in the VLS growth mode [27–29]. Usually, VLS grown Si NWs system shows complex faceting [30] including hexagonal structure [31]. Ordered arrays of planar faults were reported by Ohno *et al*. which resulted in new phases and properties of well-known materials [32]. Several researchers reported about the twinning and generation of polytype defects and their control in III-V materials based NWs [11, 12]. Generation of polytype defects in group IV-semiconductors were less explored [13, 33]. In Si NWs system {111} planar faults were confirmed along the growth axis of 〈112〉-orientation [14]. Such twin planar faults along a 〈111〉 direction, are considered as a stacking faults in the ABC stacking sequence. Ultimately, this arrangement gives rise to some local hexagonal ordering, for example, ABA, and leading to polytypes. It was also observed that isolated defects of these {111} faults of NWs can trap to the Au (gold)-catalyst atoms [34]. Such arrangements and characteristics have significant influence on the impurity distributions, electrical and optical properties of the Si NWs based nano-devices.

The defects study like twin planar defects as well as stacking fault were not rigorously investigated in the case of vertically aligned In-catalyzed (111)-oriented Si NWs. However, relatively very few investigations have been made about the stacking fault and twin planar defects in In-catalyzed Si NWs grown by VLS growth [26]. Zhan *et al*. reported the numerical study of Si NWs which discuss about the perpendicularly aligned stacking fault layers, the extrinsic stacking fault (eSF) and 9-rhombohedral (9R)-polytype [35]. Large reduction of thermal conductivity in Si NWs was induced by extrinsic stacking fault (eSF) and 9-rhombohedral (9R)-polytype, when compared to the twin boundaries and the intrinsic stacking fault (iSFs) [35]. Some single twin planes and arrays of {111} stacking faults were

**121**

*Indium (In)-Catalyzed Silicon Nanowires (Si NWs) Grown by the Vapor–Liquid–Solid (VLS)…*

The basic mechanism behind the VLS growth mode is the transformation of the solid metal catalyst nanoparticle into a liquid alloy of the catalyst and compound of the semiconductor. In this case the liquid particle acts as a privileged site for Si deposition (precipitation via liquid catalyst), and has higher sticking coefficient as compared to the solid surfaces, shown in the schematic flow mechanism of **Figure 1** [37]. Two different type of experiments were conducted to grow Si NWs. First, before the air-breaking condition p-type 300 μm-thick Cz-Si (111) substrate having resistivity of 1–10 Ω-cm, was cleaned by RCA washing. Next, In-NDs were grown on Si (111) substrate, using a conventional thermal evaporation system by evaporating pure In wire with base pressure (*P*B) of 4.4 × 10−4 Pa. Stranski–Krastanow (SK) growth mode was followed by In-NDs, which is not a two-dimensional growth, but rather gives rise to islands of the In-metal. Subsequently, the In-NDs were thermally annealed in a glass tube furnace at 630°C for 360 min and then treated by a H2 plasma at substrate temperature (*T*S) of 200°C for 30 min under a pressure of 10 Pa in a sputtering chamber (after air-breaking condition). Finally, Si NWs were grown by a radio frequency (RF) magnetron sputtering after air-breaking condition

(sample-Na) at *T*S = 630°C under pressure of 1 Pa for 30 min growth time.

In the next experiment everything was grown in the same sputtering chamber (without air-breaking condition). First, 300 μm-thick p-type Cz-Si (111) substrate, having resistivity ~1–10 Ω-cm was washed by RCA washing. Soon after RCA washing and drying the wafer was transferred to the plasma assisted and high vacuum sputtering chamber having background pressure, *P*B ~ 6.0 × 10−6 Pa. Secondly, the In-atoms were deposited on Si substrate by In-sputtering target at room temperature (RT) under working pressure of 3 Pa for 20 min. Thirdly, the as-grown In-Islands sample was treated by H2-plasma (200 sccm) in Ar (20 sccm) environment, where substrate temperature was set to 600°C, for 3 min. The heating rate of the substrate was kept 10°C/min to get self-organized and well defined In-NDs on the substrate before the Si NWs growth. Finally, the substrate temperature was set to 600°C, assisted by H2-plasma (200 sccm) in Ar (20 sccm) for 60 min under working pressure of 10 Pa and Si NWs were successfully grown (sample-Nw). The interface scenario between In-NDs and Si (111), surface morphologies, shape, density, and contact angle (θC) of In-NDs on Si-substrate were observed by high resolution scanning electron microscopy (HR-SEM). Crystal structure, i.e., cross-section, different planar defects and twining of planar defects in the entire Si NWs were observed, via selected-area of electron diffraction (SAED) as well

observed in Au-catalyzed Si NWs grown in the 〈112〉 direction [14]. Lopez *et al.* reported about such structures in Au-catalyzed 〈111〉-oriented kinked shaped Si NWs [36]. Such defects were found to be running parallel to the 〈112〉 NW axis, and often extending in the entire length of the wire. There is no report about the stacking fault as well as planar defects (twin planar defects) along 〈112〉 direction in the case of In-catalyzed, vertically aligned, and (111)-oriented Si NWs grown by VLS mode. Our main objective is to control the verticality of p-type Si NWs for the applications of nano-devices. We also investigate about the single Si NW, whether it contains twining defects, planar defects as well as stacking fault along the growth direction of In-catalyzed Si NWs. Second, we attempted to present one simple model about the root cause of stacking faults formation that are distributed around the Si NWs as well as at the interface of In-NDs/Si-substrate (polytypes). Finally, it was established that the Si NWs height were also restricted by the In-NPs migration

*DOI: http://dx.doi.org/10.5772/intechopen.97723*

from the top of the Si NWs.

**2. Experimental methods**

**Figure 1.** *Schematic flow mechanisms of In-catalyzed Si NWs grown by VLS growth mode.*

*Indium (In)-Catalyzed Silicon Nanowires (Si NWs) Grown by the Vapor–Liquid–Solid (VLS)… DOI: http://dx.doi.org/10.5772/intechopen.97723*

observed in Au-catalyzed Si NWs grown in the 〈112〉 direction [14]. Lopez *et al.* reported about such structures in Au-catalyzed 〈111〉-oriented kinked shaped Si NWs [36]. Such defects were found to be running parallel to the 〈112〉 NW axis, and often extending in the entire length of the wire. There is no report about the stacking fault as well as planar defects (twin planar defects) along 〈112〉 direction in the case of In-catalyzed, vertically aligned, and (111)-oriented Si NWs grown by VLS mode. Our main objective is to control the verticality of p-type Si NWs for the applications of nano-devices. We also investigate about the single Si NW, whether it contains twining defects, planar defects as well as stacking fault along the growth direction of In-catalyzed Si NWs. Second, we attempted to present one simple model about the root cause of stacking faults formation that are distributed around the Si NWs as well as at the interface of In-NDs/Si-substrate (polytypes). Finally, it was established that the Si NWs height were also restricted by the In-NPs migration from the top of the Si NWs.
