**2. Device structure and simulation methods**

All the simulation works were performed using Sentaurus TCAD [18]. Drift diffusion transport equations were calculated self-consistently with Poisson and electron/hole continuity equations. Density-gradient model was adopted for the quantum confinement of carriers within the channel. Slotboom bandgap narrowing model was used to consider the doping-dependent energy bandgap. Mobility models include Lombardi for the mobility degradation at the channel/oxide interface, inversion and accumulation layer model for impurity, phonon, and surface roughness scatterings, and low-field ballistic model for quasi-ballistic effects in ultra-short gate length (Lg). Shockley-Read-Hall, Auger, and Hurkx band-to-band tunneling recombination models were adopted. Deformation potential model was used to consider the stress-induced energy bandgap, effective mass, and effective density-of-states. All these physical models were used equivalently in [19, 20].

**Figure 1** shows the schematic diagrams of FinFETs and three-stacked GAAFETs. FinFETs have highly-doped punch-through-stopper (PTS) at 2 × 1018 and 4 × 1018 cm−3 for NFETs and PFETs, respectively, in order to prevent the sub-fin leakage currents at off state [21, 22]. GAAFETs, on the other hand, have buried oxide (BOX) layer beneath the source/drain (S/D) regions without PTS so that the bottom leakage currents are completely blocked [1, 23]. Bulk FinFETs can adopt the BOX layer according to [24], but the conventional device structure

#### **Figure 1.**

*Schematic diagrams of FinFETs and GAAFETs. 2-D cross-sections of nanosheet and nanowire channels were also specified to the right.*

**159**

**Table 1.**

*Geometrical parameters and values of FinFETs and GAAFETs.*

*Gate-All-Around FETs: Nanowire and Nanosheet Structure*

was considered in this work. S/D doping concentrations of the n-type and p-type devices are 2 × 1020 and 4 × 1020 cm−3, respectively. Interfacial layer (IL), HfO2, and low-k spacer regions have the dielectric constants of 3.9, 22.0, and 5.0, respectively. Contact resistivity at S/D and silicide interface is fixed to 10−9 Ω·cm2

Equivalent oxide thickness (EOT) is 1.0 nm, which consists of 0.7-nm-thick IL and

**Table 1** shows the geometrical parameters and values of 3-nm-node FinFETs and GAAFETs. Contacted poly pitch (CPP) and fin pitch (FP) are 42 and 21 nm, following 3-nm technology node [5]. There are two types of GAAFETs: nanowire FETs (NWFETs) having the same width and thickness as WNW, and nanosheet FETs (NSFETs) having thin NS thickness (TNS) of 5 nm but wide NS width (WNS) as 10, 20, 30, 40, and 50 nm. The number of NW or NS channels (Nch) is varied as

**Figure 2** shows the schematic process flows of GAAFETs. The detailed gate-las process flows are described in [1]. After depositing Si0.7Ge0.3/Si multi-layer and etching like fin structure, poly-Si gate and low-k regions are formed. Inner-spacer is formed by etching sidewalls of Si0.7Ge0.3 regions selectively and depositing low-k regions. Followed by depositing BOX layer, selective epitaxial growth of S/D regions is performed. After removing poly-Si gate, channel release process is performed by etching Si0.7Ge0.3 regions selectively. Replacement metal gate, silicidation, and metal

All the TCAD results were calibrated to Intel 10-nm node FinFETs [15]. Detailed calibration flows are as follows. Geometrical parameters such as Lg, fin width (Wfin), fin height (Hfin), CPP, and FP were referred from [15]. Subthreshold characteristics such as subthreshold swing (SS) and drain-induced barrier lowering (DIBL) were fitted by changing annealing temperature and time for proper S/D doping profiles. Saturation velocity was tuned to fit the drain current (*Ids*) in the saturation region, whereas minimum low-field mobility and ballistic coefficient were varied to fit the *Ids* in the linear region. Some parameters related to surface roughness scatterings were also modified to fit the *Ids* in the strong inversion region accordingly. These calibration flows were equivalent as in [26]. After calibration, FinFETs were scaled down to the 3-nm node for comparison with GAAFETs.

**Geometrical parameters Values** CPP Contacted poly pitch 42 nm FP Fin pitch 21 nm NP Nanowire/sheet pitch WNW or WNS + 16 nm Lg Gate length 12 nm Lsp Spacer length 5 nm Wfin Fin width 5 nm Hfin Fin height 46 nm WNW Nanowire width 5, 6, 7, 8, 9, 10 nm WNS Nanosheet width 10, 20, 30, 40, 50 nm TNS Nanosheet thickness 5 nm TSP Nanowire/sheet spacing 10 nm Nch The number of channels 1, 2, 3, 4, 5

[25].

*DOI: http://dx.doi.org/10.5772/intechopen.94060*

contact formations are done afterwards.

1.7-nm-thick HfO2.

1, 2, 3, 4, and 5.

*Nanowires - Recent Progress*

middle-of-line levels.

high performance (HP) applications.

**2. Device structure and simulation methods**

All these physical models were used equivalently in [19, 20].

**Figure 1** shows the schematic diagrams of FinFETs and three-stacked GAAFETs. FinFETs have highly-doped punch-through-stopper (PTS) at 2 × 1018 and 4 × 1018 cm−3 for NFETs and PFETs, respectively, in order to prevent the sub-fin leakage currents at off state [21, 22]. GAAFETs, on the other hand, have buried oxide (BOX) layer beneath the source/drain (S/D) regions without PTS so that the bottom leakage currents are completely blocked [1, 23]. Bulk FinFETs can adopt the BOX layer according to [24], but the conventional device structure

*Schematic diagrams of FinFETs and GAAFETs. 2-D cross-sections of nanosheet and nanowire channels were* 

is needed to set the device guideline by considering fine TCAD calibration and

Therefore, in this work, DC/AC performances of 3-nm-node GAAFETs were investigated using fully-calibrated TCAD platform. By changing the GAA geometries, we found optimal GAA structure to minimize the RC delay for three different applications such as low power (LP), standard performance (SP), and

All the simulation works were performed using Sentaurus TCAD [18]. Drift diffusion transport equations were calculated self-consistently with Poisson and electron/hole continuity equations. Density-gradient model was adopted for the quantum confinement of carriers within the channel. Slotboom bandgap narrowing model was used to consider the doping-dependent energy bandgap. Mobility models include Lombardi for the mobility degradation at the channel/oxide interface, inversion and accumulation layer model for impurity, phonon, and surface roughness scatterings, and low-field ballistic model for quasi-ballistic effects in ultra-short gate length (Lg). Shockley-Read-Hall, Auger, and Hurkx band-to-band tunneling recombination models were adopted. Deformation potential model was used to consider the stress-induced energy bandgap, effective mass, and effective density-of-states.

**158**

**Figure 1.**

*also specified to the right.*

was considered in this work. S/D doping concentrations of the n-type and p-type devices are 2 × 1020 and 4 × 1020 cm−3, respectively. Interfacial layer (IL), HfO2, and low-k spacer regions have the dielectric constants of 3.9, 22.0, and 5.0, respectively. Contact resistivity at S/D and silicide interface is fixed to 10−9 Ω·cm2 [25]. Equivalent oxide thickness (EOT) is 1.0 nm, which consists of 0.7-nm-thick IL and 1.7-nm-thick HfO2.

**Table 1** shows the geometrical parameters and values of 3-nm-node FinFETs and GAAFETs. Contacted poly pitch (CPP) and fin pitch (FP) are 42 and 21 nm, following 3-nm technology node [5]. There are two types of GAAFETs: nanowire FETs (NWFETs) having the same width and thickness as WNW, and nanosheet FETs (NSFETs) having thin NS thickness (TNS) of 5 nm but wide NS width (WNS) as 10, 20, 30, 40, and 50 nm. The number of NW or NS channels (Nch) is varied as 1, 2, 3, 4, and 5.

**Figure 2** shows the schematic process flows of GAAFETs. The detailed gate-las process flows are described in [1]. After depositing Si0.7Ge0.3/Si multi-layer and etching like fin structure, poly-Si gate and low-k regions are formed. Inner-spacer is formed by etching sidewalls of Si0.7Ge0.3 regions selectively and depositing low-k regions. Followed by depositing BOX layer, selective epitaxial growth of S/D regions is performed. After removing poly-Si gate, channel release process is performed by etching Si0.7Ge0.3 regions selectively. Replacement metal gate, silicidation, and metal contact formations are done afterwards.

All the TCAD results were calibrated to Intel 10-nm node FinFETs [15]. Detailed calibration flows are as follows. Geometrical parameters such as Lg, fin width (Wfin), fin height (Hfin), CPP, and FP were referred from [15]. Subthreshold characteristics such as subthreshold swing (SS) and drain-induced barrier lowering (DIBL) were fitted by changing annealing temperature and time for proper S/D doping profiles. Saturation velocity was tuned to fit the drain current (*Ids*) in the saturation region, whereas minimum low-field mobility and ballistic coefficient were varied to fit the *Ids* in the linear region. Some parameters related to surface roughness scatterings were also modified to fit the *Ids* in the strong inversion region accordingly. These calibration flows were equivalent as in [26]. After calibration, FinFETs were scaled down to the 3-nm node for comparison with GAAFETs.


#### **Table 1.**

*Geometrical parameters and values of FinFETs and GAAFETs.*

**Figure 2.**

*Process flows of GAAFETs. Key process schemes of GAAFETs are Si0.7Ge0.3/Si multi-layer stacking, inner-spacer formation, and channel release by etching Si0.7Ge0.3 regions selectively.*
