ZnO Nanowire Field-Effect Transistor for Biosensing: A Review

*Nonofo Mathiba Jack Ditshego*

## **Abstract**

The last 19 years have seen intense research made on zinc oxide (ZnO) material, mainly due to the ability of converting the natural n-type material into p-type. For a long time, the p-type state was impossible to attain and maintain. This chapter focuses on ways of improving the doped ZnO material which acts as a channel for nanowire field-effect transistor (NWFET) and biosensor. The biosensor has specific binding which is called functionalization that is achieved by attaching a variety of compounds on the designated sensing area. Reference electrodes and buffers are used as controllers. Top-down fabrication processes are preferred over bottom-up because they pave way for mass production. Different growth techniques are reviewed and discussed. Strengths and weaknesses of the FET and sensor are also reviewed.

**Keywords:** zinc oxide (ZnO), semiconductor device, nanosensor, nanowire field-effect transistor (NWFET), biosensors, growth techniques

### **1. Introduction**

Zinc oxide (ZnO) material has been known as a semiconductor for over 70 years, with some of the first literature being reported as early as in 1944 [1]. It was never put to use like other semiconductors (GaN, Si) because it is difficult to dope. The past 19 years have seen a revival on the research and use of material because of new and emerging ways of doping it. The material is naturally n-type [1–4], and by controlling the conditions of growth, the donor concentration can be controlled. The growth conditions include temperature, diethyl zinc (DEZ) reactant, O2 or H2O reactant, and pressure. P-type material [1–4] is difficult to grow and tends to slowly revert back to n-type. Researchers [5–14] who managed to deposit the p-type material have shown that it converts back to n-type within a few days. Maximum time period shown on p-type ZnO was a few months [5–14].

ZnO is a wide bandgap semiconductor [e.g., (0 K) = (3.441 ± 0.003) eV; (300 K) = (3.365 ± 0.005) eV]. It belongs to the group of II<sup>b</sup> -VI compound semiconductors which crystalize exclusively in the hexagonal wurtzite-type structure. The lattice parameters of the wurtzite crystal structure are: *a* = 3.24 Å and *c* = 5.21 Å. Related to similar IIb -VI (e.g., CbS, CbSe, ZnSe, and ZnS) or III-V (e.g., AlSb, Bas, GaN, and InSb) semiconductors, it has comparatively strong polar binding and large exciton binding energy of (59.5 ± 0.5) meV. Its density is 5.6 g cm−3, a value which corresponds to 4.2 × 1022 ZnO molecules per cm−3 [1, 2].

ZnO has practical advantages that make it an attractive semiconductor from an industrial point of view. It has low cost; is abundant, nontoxic, and transparent; has large excitonic binding energy of 60 meV; is soluble, compatible with intercellular material; and has wide and direct bandgap of 3.37 eV, making it highly sensitive. It is well known that semiconductors have a small bandgap which allows switching between conduction and off-states. The larger the bandgap, the better the semiconductor is able to switch states and insulate leakage currents. Bandgap affects sensitivity because a device that possesses a wider bandgap allows for higher currents to travel but also prevents leakage currents, which results in more sensitive and accurate readings. With low-temperature fabrication processes, high-quality devices can be fabricated using the conventional processing technology, thereby making it suitable for low-cost mass-production. It has potential applications in optoelectronics, transparent electronics, and spintronics. ZnO and its alloys have versatile electrical and optical properties for applications in thin film or nanowire transistors, light emitters, biosensors, and solar cells. The nanowire biosensor has a high surfaceto-volume ratio, enabling real-time and label-free detection [1–4, 15–17].

Currently, the main commercial application for ZnO (and/or IGZO) material is in displays, with companies like Sharp and Samsung putting IGZO into mobile phone displays [18–20]. IGZO displays outperform other semiconductor displays such as amorphous silicon and organic semiconductors by providing improved resolution and reduced power consumption. This is possible because IGZO has a 20× to 50× times higher mobility than amorphous silicon and polymers, which allows for device scaling without affecting performance [18–20]. Higher mobility values can also be achieved with amorphous silicon technology, but it needs to be laser annealed which is expensive.

### **2. Growth techniques of ZnO**

ZnO films can be grown using three methods: gas transport (vapor phase deposition), hydrothermal synthesis, and/or melt process. Melt growth techniques are a problem due to high vapor pressure of ZnO. Growth using gas transport is difficult to control for large film layers and is normally used for bottom-up ZnO nanostructures. Hydrothermal synthesis is therefore preferred as a method of growth. Thin films can be produced through chemical vapor deposition, metalorganic vapor phase epitaxy, electrodeposition, pulsed laser deposition, sputtering, sol–gel synthesis, atomic layer deposition, spray pyrolysis, etc. All the mentioned techniques fall under hydrothermal synthesis, and one of the preferred methods is atomic layer deposition (ALD). The ALD process is capable of producing highly conformal and quality films [21]. The process is cyclic and is based on the number of reactants. **Figure 1** shows that the ALD process for ZnO films is cyclic and depends on two reactants: metallization and oxidation.

Metallization uses diethyl zinc (DEZ) as the zinc (Zn) metal precursor. Purge and pump steps are used to separate the execution of the reactants and to remove by-products. Before deposition, the wafer (substrate) is preheated at a temperature that will be used for deposition and it is also cleaned with O2 plasma so as to remove any polymer layer. During the metallization step, the DEZ (Zn (C2H5)2) is absorbed onto the surface of the wafer and the residual Zn (C2H5)2 is removed from chamber. "R" in **Figure 1** represents C2H5.Then on another step, water or O2 is delivered to react with the absorbed DEZ [23–25]. These steps are executed separately, and to ensure this, purge steps are introduced in between the steps.

When water is used instead of O2 for oxidation, the process is called thermal ALD. This process tends to produce films similar to chemical vapor deposition (CVD)

**5**

**Figure 1.**

*with Ar step [22].*

*ZnO Nanowire Field-Effect Transistor for Biosensing: A Review*

techniques [25–27]. When O2 is used instead of water, then the process needs plasma energy. Remote plasma atomic layer deposition (RPALD) is a fairly new process which is why it is still not in used. It is better than the other deposition techniques as it tends to produce films close to epitaxial layers. The layers are crystalline but tend to be nonuniform to the underlining layer which is why they are not called epitaxial layers. It is a process with great potential for depositing highly conformal and quality films. The process is better than thermal ALD in terms of conformity and quality, but both processes do not generally produce epitaxial layers due to nonuniformity to the underlining substrate. The plasma-assisted ALD method has the following advantages: reduction of OH impurity, allows more freedom in processing conditions, and provides wider range of material properties. The OH impurity is not desired as it affects the conductivity of the semiconductor and induces defects in the dielectrics. **Table 1** compares various growth techniques and how they affect NWFET output characteristics. Chemical vapor deposition (CVD) is the most popular technique for bottom-up nanowire processes. There are two growth techniques classified under CVD which are vapor–liquid–solid (VLS) and vapor–solid (VS) deposition techniques. CVD normally give the highest mobility as they produce crystalline wires with the only flaw being from the catalysts that guide the growth. VS produces better quality nanowires than VLS as it uses no catalysts but instead uses very high temperatures (>900°C). The problem with VS is that it is usually

*Schematic diagram illustrating a single cycle of ZnO deposition using the ALD tool (A) metallisation and oxidation step, (B) Purge and pump step (C) Cleaning with O2 plasma step, (D) Removing non-used products* 

harder to control the size and morphology of the nanowires.

*DOI: http://dx.doi.org/10.5772/intechopen.93707*

*ZnO Nanowire Field-Effect Transistor for Biosensing: A Review DOI: http://dx.doi.org/10.5772/intechopen.93707*

#### **Figure 1.**

*Nanowires - Recent Progress*

laser annealed which is expensive.

**2. Growth techniques of ZnO**

reactants: metallization and oxidation.

ensure this, purge steps are introduced in between the steps.

ZnO has practical advantages that make it an attractive semiconductor from an industrial point of view. It has low cost; is abundant, nontoxic, and transparent; has large excitonic binding energy of 60 meV; is soluble, compatible with intercellular material; and has wide and direct bandgap of 3.37 eV, making it highly sensitive. It is well known that semiconductors have a small bandgap which allows switching between conduction and off-states. The larger the bandgap, the better the semiconductor is able to switch states and insulate leakage currents. Bandgap affects sensitivity because a device that possesses a wider bandgap allows for higher currents to travel but also prevents leakage currents, which results in more sensitive and accurate readings. With low-temperature fabrication processes, high-quality devices can be fabricated using the conventional processing technology, thereby making it suitable for low-cost mass-production. It has potential applications in optoelectronics, transparent electronics, and spintronics. ZnO and its alloys have versatile electrical and optical properties for applications in thin film or nanowire transistors, light emitters, biosensors, and solar cells. The nanowire biosensor has a high surface-

to-volume ratio, enabling real-time and label-free detection [1–4, 15–17].

Currently, the main commercial application for ZnO (and/or IGZO) material is in displays, with companies like Sharp and Samsung putting IGZO into mobile phone displays [18–20]. IGZO displays outperform other semiconductor displays such as amorphous silicon and organic semiconductors by providing improved resolution and reduced power consumption. This is possible because IGZO has a 20× to 50× times higher mobility than amorphous silicon and polymers, which allows for device scaling without affecting performance [18–20]. Higher mobility values can also be achieved with amorphous silicon technology, but it needs to be

ZnO films can be grown using three methods: gas transport (vapor phase deposition), hydrothermal synthesis, and/or melt process. Melt growth techniques are a problem due to high vapor pressure of ZnO. Growth using gas transport is difficult to control for large film layers and is normally used for bottom-up ZnO nanostructures. Hydrothermal synthesis is therefore preferred as a method of growth. Thin films can be produced through chemical vapor deposition, metalorganic vapor phase epitaxy, electrodeposition, pulsed laser deposition, sputtering, sol–gel synthesis, atomic layer deposition, spray pyrolysis, etc. All the mentioned techniques fall under hydrothermal synthesis, and one of the preferred methods is atomic layer deposition (ALD). The ALD process is capable of producing highly conformal and quality films [21]. The process is cyclic and is based on the number of reactants. **Figure 1** shows that the ALD process for ZnO films is cyclic and depends on two

Metallization uses diethyl zinc (DEZ) as the zinc (Zn) metal precursor. Purge and pump steps are used to separate the execution of the reactants and to remove by-products. Before deposition, the wafer (substrate) is preheated at a temperature that will be used for deposition and it is also cleaned with O2 plasma so as to remove any polymer layer. During the metallization step, the DEZ (Zn (C2H5)2) is absorbed onto the surface of the wafer and the residual Zn (C2H5)2 is removed from chamber. "R" in **Figure 1** represents C2H5.Then on another step, water or O2 is delivered to react with the absorbed DEZ [23–25]. These steps are executed separately, and to

When water is used instead of O2 for oxidation, the process is called thermal ALD.

This process tends to produce films similar to chemical vapor deposition (CVD)

**4**

*Schematic diagram illustrating a single cycle of ZnO deposition using the ALD tool (A) metallisation and oxidation step, (B) Purge and pump step (C) Cleaning with O2 plasma step, (D) Removing non-used products with Ar step [22].*

techniques [25–27]. When O2 is used instead of water, then the process needs plasma energy. Remote plasma atomic layer deposition (RPALD) is a fairly new process which is why it is still not in used. It is better than the other deposition techniques as it tends to produce films close to epitaxial layers. The layers are crystalline but tend to be nonuniform to the underlining layer which is why they are not called epitaxial layers. It is a process with great potential for depositing highly conformal and quality films. The process is better than thermal ALD in terms of conformity and quality, but both processes do not generally produce epitaxial layers due to nonuniformity to the underlining substrate. The plasma-assisted ALD method has the following advantages: reduction of OH impurity, allows more freedom in processing conditions, and provides wider range of material properties. The OH impurity is not desired as it affects the conductivity of the semiconductor and induces defects in the dielectrics.

**Table 1** compares various growth techniques and how they affect NWFET output characteristics. Chemical vapor deposition (CVD) is the most popular technique for bottom-up nanowire processes. There are two growth techniques classified under CVD which are vapor–liquid–solid (VLS) and vapor–solid (VS) deposition techniques. CVD normally give the highest mobility as they produce crystalline wires with the only flaw being from the catalysts that guide the growth. VS produces better quality nanowires than VLS as it uses no catalysts but instead uses very high temperatures (>900°C). The problem with VS is that it is usually harder to control the size and morphology of the nanowires.


**7**

**No**

15 16 17 18 **Table 1.**

ALD Plasma ALD *Summary of various methods used for the production of 1-D ZnO nanostructures, adopted from [28].*

DEZ (Zn (C

DEZ (Zn (C

H2

5)2), O2

H2 5)2), H

O2

—

150–190

Nanowire

Nanowire

70–100 36–100

5 μm 2–20 μm

[22]

**Processing route**

**Synthesis method**

**Starting materials**

Zn(NO3)2·6H

O, NaOH, 2 cyclohexylamine, ethanol, water

200

Nanorod

150–200

Zn(SO4)·7H O, NH 2

OH, deionized 4

75–95

Nanorod

—

—

[43]

 water

**Synthesis temp. (°C)**

**Morphology**

**Diameter of ZnO nanostructure (mm)**

**Length of ZnO nanostructure**

**Ref.**

2 μm

[42]

*ZnO Nanowire Field-Effect Transistor for Biosensing: A Review*

*DOI: http://dx.doi.org/10.5772/intechopen.93707*

[44]

*Nanowires - Recent Progress*


**Table 1.** *Summary of various methods used for the production of 1-D ZnO nanostructures, adopted from [28].*

*ZnO Nanowire Field-Effect Transistor for Biosensing: A Review DOI: http://dx.doi.org/10.5772/intechopen.93707*

*Nanowires - Recent Progress*

**6**

**No**

1 2 3 4 5 6 7 8 9

Solid-state

Carbothermal

reduction

processing

10 11 12

Wet

Hydrothermal

ZnAc2, NaOH, absolute ethanol,

180

Nanorod

distilled water

Zn(CH COO) 3

2·2H O, C 2 absolute ethanol, distilled water

Zn(NO3)2·6H cetyltrimethyl ammonium bromide,

ethanol

O, NaOH, 2

120

Nanorod

—

—

[41]

H6 O8 7·H O, 2

400

Nanorod

50

500 nm

[40]

(vertically

aligned)

processing

13 14

Route

Route

Solid-state

Chemical

Reaction

RF sputtering Molecular beam

epitaxy

ZnO deposited over Pt sputtered

—

Nanobelt

interdigitated alumina substrate

Zn metal, O3/O2 plasma discharge,

600

Nanorod

50–150

2–10 μm

[35]

Au coated substrate

ZnO powder, graphite powder, Ar

900–925

Nanowire

80–120

10–20 μm

[36,

37]

gas flow, Au coated silicon substrate

ZnCl2, NaOH, polyethylene Glycol,

RT

Nanorod

40–60 20–40

—

100 nm

—

[39]

200 nm

[38]

Na WO 2

4.2H

O2

Vapor phase

transport

Aerosol

Zn powder, N2 gas

500–750

Fiber-mat Cauliflower

100–300

20–30

—

—

—

Few micrometer

[34]

[33]

Route

Vapor phase

Thermal

Zn metal, O2, and Ar

Zn metal pellets, O2, Ar

Zn powder, O2, Ar

ZnO powder, graphite, Cu catalyst

930

Hierarchical

dendrite

900 600

Nanowire

Nanowire

20

80 60–800

—

1 μm

—

[32]

[31]

[30]

evaporation

processing

**Processing** 

**Synthesis** 

**Starting materials**

**Synthesis** 

**Morphology**

**Diameter of ZnO** 

**Length of ZnO** 

**Ref.**

**nanostructure**

Several microns

[29]

**nanostructure (mm)**

100

**temp. (°C)**

650–670

Nanowire

**method**

**route**

**Table 1** also shows that atomic layer deposition (ALD) is an attractive technique because it deposits high quality films at low temperatures between 120 and 210°C [22, 45]. The problem with ALD is that it has only this window for good quality conducting films. At temperatures below 120°C, the deposition can be incomplete or experience condensation depending on growth rate. At temperatures above 210°C, the deposition tends to experience desorption or it decomposes toward CVD deposition. Nonetheless, it is one of the best techniques toward growing films close to epitaxial growth (crystallinity is achievable whereas uniformity is still difficult to achieve) [22, 45]. The tool has shown potential by achieving high values of field effect mobility >30 cm2 /Vs with excellent crystallinity.

## **2.1 Native point defects**

There are three types of defects in a crystal lattice: point defects, area defects, and volume defects. Point defects which are caused by native elements and impurities are the major problem for ZnO semiconductor. Native point defects for ZnO include the following: zinc interstitial (Zni), zinc antisite (Zno), zinc vacancy (VZn), oxygen interstitial (Oi), oxygen antisite (OZn), and oxygen vacancy (Vo). Over the years, a lot of research advocated them as the major cause for the n-type behavior. Oxygen defects are seen as the main contributors toward the n-type behavior [3, 15]. There are some researchers [1–4] who hypothesize that impurities (not the native point defects) are the main cause of the n-type behavior because they tend to be shallow donors whereas Zn and O2 defects tend to be deep donors [1–4]. The two theories have not been proven so currently the main cause of the natural n-type behavior of ZnO [1–4] is not certain.

### **2.2 Deep donors versus shallow donors: ZnO**

ZnO impurities (foreign atoms) are normally incorporated in the crystal structure of the semiconductor. There are two reasons of impurity incorporation: they can either be unintentionally introduced due to lack of control during growth processes or they are intentionally added to increase the number of free carriers in the semiconductor. Impurities in the ZnO should have the ability to be ionized; which is desirable as it increases conductivity. This means that the impurity atoms should be able to give off electrons to the conduction band. If the impurities were acceptors—they should be able to give off holes to the valence band [3, 16].

Donor Impurities for the n-type ZnO can either be shallow or deep. **Figure 2** shows shallow donors compared to deep donors. Shallow impurities require little energy to ionize (this is energy typically around the thermal energy or less). These donor impurities possess energy close to the band edge—the extra valence electron

**9**

**Figure 3.**

*(a) before dry etch and (b) after dry etch [22].*

*ZnO Nanowire Field-Effect Transistor for Biosensing: A Review*

**2.3 Top-down fabrication of ZnO nanowire FETs**

of these impurities are loosely bound and occupy effective-mass states near the conduction band maximum- CBM- at low temperatures. Deep impurities onthe-other-hand require energy greater that the thermal energy to ionize. These donor impurities possess energy far from the band edge (CBM) making them very hard to ionize. Their presence within the semiconductor tends to contribute only a small fraction of free carriers. Deep donors are also called traps because they act as effective recombination centers in which electrons and holes fall and annihilate each other. Grain boundaries (GB) are main source of deep state impurities and they adversely affect transistor performance. ZnO is a wide bandgap material and research suggests [3, 4, 16] that there exist possible deep-level traps in GBs. The examples of deep donors are Zn and O ions. Zn acts as a deep donor when there is a vacancy and O acts as a deep donor in any defect state. An example of a shallow

There are four main methods capable of producing nanometer features using top-down approaches: UV stepper lithography, e-beam lithography [46], focused ion-beam lithography [47], and spacer method [45, 48]. UV lithography is the standard industrial method for fabricating nanodevices. E-beam and focused ion-beam lithography are often used and can pattern devices down to 5 nm, but the equipment is very expensive and the pattern writing is very slow. These two instruments resemble scanning electron microscope (SEM) in terms of operation. Whereas SEM is used to focus a beam of electrons to image samples within a chamber, these instruments are used to create patterns on the samples. The difference between e-beam and focused ion-beam is that the latter uses an ion beam to pattern wafers and hence does not require photoresist. Their advantage over optical UV lithography is the small features they reach. For low-cost applications such as biosensors, the problem with these two methods is that they are

The spacer technique is a low-cost fabrication method for fabricating nanowires.

It was first reported in 2005 by Ge et al. [49], and other researchers [44, 50, 51] have since carried it forward. The technique has great potential in shaping nanometer features using conventional, low-cost photolithography. **Figure 3** shows the concept of the spacer technique. It uses first anisotropic etch to create a vertical pillar on an insulating layer (SiO2), then after deposition of a semiconductor layer (ZnO) and a second anisotropic etch, to create nanowires made up of the semiconductor layer. This method allows nanowire features with controllable dimensions to be developed. The ICP tool is usually used for anisotropic etching and produces

*Novel spacer technique used to pattern nanowire features. Cross-sectional schematic of nanowire formation* 

*DOI: http://dx.doi.org/10.5772/intechopen.93707*

donor is the H ion.

expensive.

**Figure 2.** *Shallow versus deep donors [1–4].*

#### *ZnO Nanowire Field-Effect Transistor for Biosensing: A Review DOI: http://dx.doi.org/10.5772/intechopen.93707*

*Nanowires - Recent Progress*

effect mobility >30 cm2

**2.1 Native point defects**

ZnO [1–4] is not certain.

band [3, 16].

**2.2 Deep donors versus shallow donors: ZnO**

**Table 1** also shows that atomic layer deposition (ALD) is an attractive technique because it deposits high quality films at low temperatures between 120 and 210°C [22, 45]. The problem with ALD is that it has only this window for good quality conducting films. At temperatures below 120°C, the deposition can be incomplete or experience condensation depending on growth rate. At temperatures above 210°C, the deposition tends to experience desorption or it decomposes toward CVD deposition. Nonetheless, it is one of the best techniques toward growing films close to epitaxial growth (crystallinity is achievable whereas uniformity is still difficult to achieve) [22, 45]. The tool has shown potential by achieving high values of field

/Vs with excellent crystallinity.

There are three types of defects in a crystal lattice: point defects, area defects, and volume defects. Point defects which are caused by native elements and impurities are the major problem for ZnO semiconductor. Native point defects for ZnO include the following: zinc interstitial (Zni), zinc antisite (Zno), zinc vacancy (VZn), oxygen interstitial (Oi), oxygen antisite (OZn), and oxygen vacancy (Vo). Over the years, a lot of research advocated them as the major cause for the n-type behavior. Oxygen defects are seen as the main contributors toward the n-type behavior [3, 15]. There are some researchers [1–4] who hypothesize that impurities (not the native point defects) are the main cause of the n-type behavior because they tend to be shallow donors whereas Zn and O2 defects tend to be deep donors [1–4]. The two theories have not been proven so currently the main cause of the natural n-type behavior of

ZnO impurities (foreign atoms) are normally incorporated in the crystal structure of the semiconductor. There are two reasons of impurity incorporation: they can either be unintentionally introduced due to lack of control during growth processes or they are intentionally added to increase the number of free carriers in the semiconductor. Impurities in the ZnO should have the ability to be ionized; which is desirable as it increases conductivity. This means that the impurity atoms should be able to give off electrons to the conduction band. If the impurities were acceptors—they should be able to give off holes to the valence

Donor Impurities for the n-type ZnO can either be shallow or deep. **Figure 2** shows shallow donors compared to deep donors. Shallow impurities require little energy to ionize (this is energy typically around the thermal energy or less). These donor impurities possess energy close to the band edge—the extra valence electron

**8**

**Figure 2.**

*Shallow versus deep donors [1–4].*

of these impurities are loosely bound and occupy effective-mass states near the conduction band maximum- CBM- at low temperatures. Deep impurities onthe-other-hand require energy greater that the thermal energy to ionize. These donor impurities possess energy far from the band edge (CBM) making them very hard to ionize. Their presence within the semiconductor tends to contribute only a small fraction of free carriers. Deep donors are also called traps because they act as effective recombination centers in which electrons and holes fall and annihilate each other. Grain boundaries (GB) are main source of deep state impurities and they adversely affect transistor performance. ZnO is a wide bandgap material and research suggests [3, 4, 16] that there exist possible deep-level traps in GBs. The examples of deep donors are Zn and O ions. Zn acts as a deep donor when there is a vacancy and O acts as a deep donor in any defect state. An example of a shallow donor is the H ion.

### **2.3 Top-down fabrication of ZnO nanowire FETs**

There are four main methods capable of producing nanometer features using top-down approaches: UV stepper lithography, e-beam lithography [46], focused ion-beam lithography [47], and spacer method [45, 48]. UV lithography is the standard industrial method for fabricating nanodevices. E-beam and focused ion-beam lithography are often used and can pattern devices down to 5 nm, but the equipment is very expensive and the pattern writing is very slow. These two instruments resemble scanning electron microscope (SEM) in terms of operation. Whereas SEM is used to focus a beam of electrons to image samples within a chamber, these instruments are used to create patterns on the samples. The difference between e-beam and focused ion-beam is that the latter uses an ion beam to pattern wafers and hence does not require photoresist. Their advantage over optical UV lithography is the small features they reach. For low-cost applications such as biosensors, the problem with these two methods is that they are expensive.

The spacer technique is a low-cost fabrication method for fabricating nanowires. It was first reported in 2005 by Ge et al. [49], and other researchers [44, 50, 51] have since carried it forward. The technique has great potential in shaping nanometer features using conventional, low-cost photolithography. **Figure 3** shows the concept of the spacer technique. It uses first anisotropic etch to create a vertical pillar on an insulating layer (SiO2), then after deposition of a semiconductor layer (ZnO) and a second anisotropic etch, to create nanowires made up of the semiconductor layer. This method allows nanowire features with controllable dimensions to be developed. The ICP tool is usually used for anisotropic etching and produces

#### **Figure 3.**

*Novel spacer technique used to pattern nanowire features. Cross-sectional schematic of nanowire formation (a) before dry etch and (b) after dry etch [22].*

surface roughness <1.5 nm. Other tools such as RIE and ion beam etch produce roughness >5 nm. The fabrication process for the complete ZnO NWFET structure is as outlined in [52].
